74HC73DB,112 NXP Semiconductors, 74HC73DB,112 Datasheet
74HC73DB,112
Specifications of 74HC73DB,112
935190270112
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74HC73DB,112 Summary of contents
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Dual JK flip-flop with reset; negative-edge trigger Rev. 04 — 19 March 2008 1. General description The 74HC73 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A pin compatible with Low-power Schottky TTL ...
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... NXP Semiconductors 4. Functional diagram Fig 1. Functional diagram 1CP CP 5 2CP Fig 2. Logic symbol 74HC73_4 Product data sheet Dual JK flip-flop with reset; negative-edge trigger FF1 1 1CP FF2 5 2CP 001aab981 001aab979 Fig 3. Rev. 04 — 19 March 2008 001aab980 IEC logic symbol © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors Fig 4. Logic diagram (one flip-flop) 5. Pinning information 5.1 Pinning Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin 1CP, 2CP GND 11 1Q, 2Q 12, 9 1Q, 2Q 13, 8 1J, 2J 14, 7 74HC73_4 Product data sheet Dual JK flip-flop with reset; negative-edge trigger ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nR nCP [ HIGH voltage level HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition LOW voltage level LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions t propagation nCP to nQ; see pd delay nCP to nQ; see nQ, nQ; see transition time nQ, nQ; see pulse width nCP input, HIGH or LOW; ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions t hold time nJ nCP; see maximum nCP input; see max frequency power per flip-flop; PD dissipation V = GND capacitance [ the same PHL PLH [ the same ...
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... NXP Semiconductors 11. Waveforms nJ, nK input nCP input nQ output nQ output The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J ...
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... NXP Semiconductors Table 8. Measurement points Type Input V I 74HC73 V CC Test data is given in Table Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Fig 8. Test circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 11. Package outline SOT337-1 (SSOP14) ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Release date 74HC73_4 20080319 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Quick reference data incorporated into • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...