AD5273 Analog Devices, AD5273 Datasheet - Page 12

• Manufacturer Part Number: AD5273
• Description: 64-Position OTP Digital Potentiometer
• Manufacturer: Analog Devices

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Note that in the zero-scale condition a fi nite wiper resistance of
60
between W and B in this state to a maximum pulse current of no
more than 20 mA. Otherwise, degradation or possible destruction
of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance R
terminals are used, terminal B can be opened. Setting the resis-
tance value for R
decreases as the data loaded in the latch increases in value. The
general equation for this operation is:
For R
resistance R
D (DEC)
63
32
1
0
The typical distribution of the nominal resistance R
to channel matches within ±1%. Device-to-device matching is
process lot dependent and is possible to have ±30% variation.
Voltage Output Operation
Similar to the D/A converter, the digital potentiometer easily
generates a voltage divider at wiper-to-B and wiper-to-A to be
proportional to the input voltage at A–B. Unlike the polarity of
V
can be at either polarity as long as the voltage across them is < IV
If ignoring the effect of the wiper resistance for approximation,
connecting terminal A to 5 V and terminal B to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 5 V. Each
LSB of voltage is equal to the voltage applied across terminal A–B,
divided by the 63 position of the potentiometer divider as:
AD5273
DD
, which must be positive, voltage across A–B, W–A, and W–B
V
R
is present. Care should be taken to limit the current fl ow
AB
W
WA
( )
= 10 k and terminal B is opened, the following output
D
( )
D
WA
=
=
Figure 3. Equivalent RDAC Circuit
will be set for the following RDAC latch codes.
63
D
R
60
4980
9901
10060
63
WA
WA
V
63
–
D5
D4
D3
D2
D1
D0
DECODER
starts at a maximum value of resistance and
A
( )
LATCH
D
RDAC
AND
¥
R
AB
+
Output State
Full-Scale
Midscale
1 LSB
Zero-Scale
R
R
R
R
S
S
S
W
A
W
B
WA
AB
. When these
from channel
DD
(2)
(3)
I.
–12–
3-terminal digital potentiometer operation. Supply signals present
on terminals A, B, and W that exceed V
powered after V
For a more accurate calculation, which includes the effect of
wiper resistance, V
Operation of the digital potentiometer in the divider mode results
in a more accurate operation overtemperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
internal resistors R
fore, the temperature drift reduces to 10 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figures 4a and 4b. This
applies to digital input pins SDA and SCL.
TERMINAL VOLTAGE OPERATING RANGE
The V
internal forward-biased diodes. See Figure 5.
POWER-UP SEQUENCE
Since there are ESD protection diodes that limit the voltage compli-
ance at terminals A, B, and W (Figure 5), it is important to power
V
Otherwise, the diode will be forward-biased such that V
be powered unintentionally and may affect the rest of the users’
circuits. The ideal power-up sequence is in the following order:
GND, V
V
POWER SUPPLY CONSIDERATIONS
AD5273 employs fuse link technology, which requires an adequate
current density to blow the internal fuses to achieve a given setting.
As a result, the power supply, either an on-board linear regulator
or rack-mount power supply, must be rated at 5 V with less than
±5% tolerance. The supply should be able to handle 100 mA of
transient current, and lasts about 400 ms, during the one-time
programming. A low ESR 1 µF to 10 µF tantalum or electrolytic
DD
B
, V
V
fi rst before applying any voltage to terminals A, B, and W.
W
Figure 5. Maximum Terminal Voltages Set by V
DD
W
Figure 4b. ESD Protection of Resistor Terminals
, and digital inputs is not important as long as they are
DD
( )
of AD5273 defi nes the boundary conditions for proper
D
Figure 4a. ESD Protection of Digital Pins
, digital inputs, and V
=
R
DD
WB
R
.
W
AB
WA
( )
can be found as:
D
and R
V
A,B,W
A
340
WB
and not the absolute values, there-
A/B/W
LOGIC
. The order of powering V
V
A
W
B
GND
DD
DD
will be clamped by the
DD
DD
will
REV. 0
A
(4)
,