AD5273 Analog Devices, AD5273 Datasheet - Page 3

• Manufacturer Part Number: AD5273
• Description: 64-Position OTP Digital Potentiometer
• Manufacturer: Analog Devices

www.DataSheet4U.com
Parameter
DYNAMIC CHARACTERISTICS
INTERFACE TIMING CHARACTERISTICS (applies to all parts
INTERFACE TIMING CHARACTERISTICS (applies to all parts
NOTES
10
11
12
13
Specifications subject to change without notice.
REV. 0
1
2
3
4
5
6
7
8
9
Typicals represent average readings at 25°C, V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
V
V = V
INL and DNL are measured at V
INL and DNL are measured at V
INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Different from operating power supply, power supply for OTP is used one time only.
Different from operating current, supply current for OTP lasts approximately 400 ms for one time needed only.
P
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
All dynamic characteristics use V
Different from settling time after fuses are blown. The OTP settling time occurs once only.
See Figure 1 for location of measured values.
Bandwidth –3 dB
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time
Power-Up Settling Time –
Resistor Noise Voltage
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
AB
AB
DISS
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
R
R
SU;STO
Post Fuses Blown
STOP and START
(repeated START)
Condition
SCL Signals
SCL Signals
Condition
Fall Time of Both SDA and
Rise Time of Both SDA and
Rise Time of Both SDA and
is calculated from (I
Bus Free Time between
Low Period of SCL Clock
DD
High Period of SCL Clock
Setup Time for START
Setup Time for STOP
, Wiper (V
Hold Time
Data Setup Time
Data Hold Time
W
) = No Connect.
DD
12
 V
W
W
W
W
DD
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter.V = V
). CMOS logic level inputs result in minimum power dissipation.
= 5 V.
6, 10, 11
DD
= 5 V, V
Symbol
BW_1 k
BW_10 k
BW_50 k
BW_100 k R
THD
t
t
t
e
f
f
f
t
t
t
t
t
t
t
t
t
t
S2
SCL
SCL
SCL
SCL
1
2
3
4
5
6
7
8
9
10
S1
S_OTP
N_WB
SS
W
= 0 V.
Conditions
R
R
R
V
V
V = 1 V rms, R
V
V
V
V = 5 V ± 1 LSB Error Band, V
Measured at V
V
V
V = 5 V ± 1 LSB Error Band, V
Measured at V
V
V
V = 5 V ± 1 LSB Error Band, V
Measured at V
R
R
R
R
R
R
R
R
R
R
R
R = 100 k
After this period, the first clock
pulse is generated.
A
A
A
A
A
A
A
A
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
AB
B
= 0 V, f = 1 kHz
= 100 k
= 100 k , f = 1 kHz, Code = 20
= 20 k
= 20 k
= 20 k , f = 1 kHz, Code = 20
= 50 k
= 50 k
= 50 k , f = 1 kHz, Code = 20
= 1 k, f = 1 kHz, Code = 20
= 1 k, Code = 20
= 10 k, Code = 20
= 50 k, Code = 20
= 100 k, Code = 20
–3–
6, 11, 13
W
W
W
AB
)
= 1 k,
H
H
H
H
B
B
B
H
H
H
H
= 0,
= 0,
= 0,
Min
1.3
0.6
1.3
0.6
0.6
0.1
0.6
A
A
A
A
= V
Typ
6000
600
110
60
0.014
5
400
5
3
13
20
28
DD
and V
B
Max
400
50
0.9
0.3
0.3
= 0 V. DNL specification
AD5273
Unit
kHz
kHz
kHz
kHz
%
µs
ms
µs
nV/
nV/
nV/√Hz
nV/√Hz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
√
√
√
√
√
√
√Hz
√
√Hz
√
Hz
Hz
Hz
Hz