AD5273 Analog Devices, AD5273 Datasheet - Page 14

• Manufacturer Part Number: AD5273
• Description: 64-Position OTP Digital Potentiometer
• Manufacturer: Analog Devices

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AD5273
In both Read and Write operations, the program generates the
I
and 25 for SDA_write, SCL, SDA_read, and DGND, respectively,
to control the device. See Figure 8.
To apply the device programming software in the factories, users
may lay out the AD5273 SCL and SDA pads on the PCB such
that the programming signals can be communicated to and from
the parallel port. Figure 9 shows a recommended AD5273 PCB
layout that pogo pins can be inserted for factory programming.
100
pins to prevent damaging the PC parallel port. Pull-up resistors
on SCL and SDA are also required.
For users who do not use the software solution, the AD5273 can
be controlled via an I
to this bus as a slave device. Referring to Figures 10a, 10b, and
11, the 2-wire I
1. The master initiates data transfer by establishing a START
2
Figure 9. Recommended AD5273 PCB Layout. The SCL
and SDA pads allow pogo pins to be inserted so that
signals can be communicated through the parallel port
for programming. Refer to Figure 8.
C digital signals through the parallel port LPT1 pins 2, 3, 15,
Figure 8. Parallel Port Connection. Pin 2 = SDA_write,
Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND
condition, which is when SDA goes from high to low while
SCL is high, Figure 10a. The following byte is the Slave
resistors should also be put in series to the SCL and SDA
2
C serial bus protocol operates as follows:
2
C compatible serial bus and is connected
DGND
SCL
V
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
DD
W
100
R3
100
100
R2
R1
R4
10k
WRITE
V
SCL
READ
DD
A
B
A0
SDA
R5
10k
SDA
–14–
2. A Write operation contains one more Instruction byte than the
3. In the Read mode, the Data byte follows immediately after the
4. When all data bits have been read or written, a STOP condi-
A repeated Write function gives the user fl exibility to update the
RDAC output a number of times, except after permanent pro-
gramming, after addressing and instructing the part only once.
During the Write cycle, each data byte will update the RDAC
output. For example, after the RDAC has acknowledged its Slave
Address and Instruction bytes, the RDAC output will update after
these two bytes. If another byte is written to the RDAC while it is
still addressed to a specifi c slave device with the same instruction,
this byte will update the output of the selected slave device. If dif-
ferent instructions are needed, the Write mode has to be started
with a new Slave Address, Instruction, and Data bytes again.
Similarly, a repeated Read function of the RDAC is also allowed.
The slave whose address corresponds to the transmitted
Address byte, which consists of the 6 MSBs as slave address
defi ned as 010110. The next bit is AD0; it is an I
address bit. Depending on the states of their AD0 bits, two
AD5273s can be addressed on the same bus. (See Figure 12.)
The last LSB is the R/
will be read from or written to the slave device.
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register.
Read operation. The Instruction byte in the Write mode fol-
lows the Slave Address byte. The MSB of the Instruction byte
labeled T is the One Time Programming bit. After acknowl-
edging the Instruction byte, the last byte in the Write mode
is the Data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
Acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL. See Figure 10a.
acknowledgment of the Slave Address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (slight dif-
ference with the Write mode, there are eight data bits followed
by a No Acknowledge bit). Similarly, the transitions on the SDA
line must occur during the low period of SCL and remain
stable during the high period of SCL as shown in Figure 11.
tion is established by the master. A STOP condition is defi ned
as a low-to-high transition on the SDA line while SCL is high.
In the Write mode, the master will pull the SDA line high
during the tenth clock pulse to establish a STOP condition,
Figures 10a and 10b. In the Read mode, the master will issue
a No Acknowledge for the ninth clock pulse, i.e., the SDA
line remains high. The master will then bring the SDA line
low before the tenth clock pulse which goes high to establish a
STOP condition. See Figure 11.
bit, which determines whether data
2
C device
REV. 0