LT1720 Linear Technology, LT1720 Datasheet - Page 18

• Manufacturer Part Number: LT1720
• Description: 4ns/ 150MHz Dual Comparator with Independent Input/Output Supplies
• Manufacturer: Linear Technology

LT1720/LT1721
Optional Logarithmic Pulse Stretcher
The fourth comparator of the quad LT1721 can be put to
work as a logarithmic pulse stretcher. This simple circuit
can help tremendously if you don’t have a fast enough
oscilloscope (or control circuit) to easily capture 3ns pulse
widths (or faster). When an input pulse occurs, C2 is
charged up with a 180ns capture
hysteresis and 10mV offset across R3 are overcome
within the first nanosecond
output high. When the input pulse subsides, C2 dis-
charges with a 540ns time constant, keeping the compara-
tor on until the decay overrides the 10mV offset across R3
minus hysteresis. Because of this exponential decay, the
output pulse width will be proportional to the logarithm of
the input pulse width. It is important to bypass the circuit’s
V
keeps the quiescent input voltage in a range where forward
leakage of the diode due to the 0.4V V
comparator is not a problem.
Neglecting some effects
input pulse as:
where
t
t
V
V
V
V
18
APPLICATIONS
P
OUT
1
2
CC
OFF
H
C
CH
= input pulse width
t
= R1 || R2 • C2
= R2 • C2
= V
= 3.5mV
OUT
= V
well to avoid coupling into the resistive divider. R4
= output pulse width
= 10mV
IN
=
C
– V
–
+ t
• R2/(R1 + R2)
2
P
• l
FDIODE
1
• l
n
{V
n
[V
CH
U
CH
• [1 – exp (–t
/(V
4
, the output pulse is related to the
INFORMATION
CH
U
3
the capture time constant
the decay time constant
the voltage drop across R1
LT1721 hysteresis
the input pulse voltage after
the diode drop
the effective source voltage
for the charge
, switching the comparator
– V
OFF
P
2
W
/
– V
time constant. The
1
)]/(V
H
OL
/2)]
of the driving
OFF
U
– V
H
/2)}
(1)
For simplicity, with t
delay in turn-on due to offset and hysteresis, the equation
can be approximated by:
For example, an 8ns input pulse gives a 1.67 s output
pulse. Doubling the input pulse to 16ns lengthens the
output pulse by 0.37 s. Doubling the input pulse again to
32ns adds another 0.37 s to the output pulse, and so on.
The rate of 0.37 s per octave falls out of the above
equation as:
There is 0.01 s jitter
uncertainty referred to the input pulse of less than 2%
(60ps resolution on a 3ns pulse with a 60MHz oscillo-
scope—not bad!). The beauty of this circuit is that it gives
resolution precisely where it’s hardest to get. The jitter is
due to a combination of the slow decay of the last few
millivolts on C2 and the 4nV/ Hz noise and 400MHz
bandwidth of the LT1721 input stage. Increasing the offset
across R3 or decreasing
expense of dynamic range.
The circuit topology itself is extremely fast, limited theo-
retically only by the speed of the diode, the capture time
constant
shows results achieved with the implementation shown,
compared to a plot of equation (1). The low end is limited
by the delivery time of the upstream comparators. As the
input pulse width is increased, the log function is con-
strained by the asymptotic RC response but, rather than
becoming clamped, becomes time linear. Thus, for very
long input pulses the third term of equation (1) dominates
and the circuit becomes a 3 s pulse stretcher.
2
3
4
5
So called because the very fast input pulse is “captured,” for later examination, as a charge on the
capacitor.
Assuming the input pulse slew rate at the diode is infinite. This effective delay constant, about 0.4%
of
this effective delay will be 2ns.
V
Thevenin equivalent charge voltage seen by C2 is boosted slightly by R2 being terminated above
ground.
Output jitter increases with inputs pulse widths below ~ 3ns.
C
t
is dependent on the LT1721 output voltage and nonlinear diode characteristics. Also, the
1
OUT
or 0.8ns, is the second term of equation 1, below. Driven by the 2.5ns slew-limited LT1721,
t
OUT
=
/octave =
2
1
• l
and the pulse source impedance. Figure 14
n
[(V
2
CH
P
• l
5
<
• t
in the output pulse which gives an
n
P
(2)
1
, and neglecting the very slight
/
2
1
will decrease this jitter at the
)/(V
OFF
– V
H
/2)]
(2)
(3)