LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 19

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

A
CLK. V
portional to f
generate a 1/4LSB error (5mV) with the converter running
at CLK = 12MHz, its peak value would have to be 18.7V.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1196/
LTC1198 have one capacitive switching input current
spike per conversion. These current spikes settle quickly
and do not cause a problem. However, if source resis-
tances larger than 100 are used or if slow settling op
amps drive the inputs, care must be taken to insure that the
transients caused by the current spikes settle completely
before the conversion begins.
PPLICATI
ERROR
“+” INPUT
“–” INPUT
D
CLK
OUT
D
CS
IN
CLK
is proportional to f(“–”) and inversely pro-
O
. For a 60Hz signal on the “–” input to
U
S
I FOR ATIO
U
START
Figure 7. LTC1198 “+” and “–” Input Settling Windows
W
SGL/DIFF
U
ODD/SIGN
SAMPLE
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
DUMMY
“+” Input Settling
The input capacitor of the LTC1196 is switched onto “+”
input at the end of the conversion and samples the input
signal until the conversion begins (see Figure 1). The input
capacitor of the LTC1198 is switched onto “+” input during
the sample phase (t
is 2.5 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within t
LTC1196/LTC1198. Minimizing R
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
allowing more time between conversions for the LTC1196
or by using a slower CLK frequency for the LTC1198.
“+” INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
DUMMY
HOLD
SMPL
, see Figure 7). The sample phase
t
CONV
DON’T CARE
LTC1196/LTC1198
SOURCE
1196/98 F07
B7
+
will improve
SMPL
19
for the