LTC1196-1BC Linear Technology, LTC1196-1BC Datasheet - Page 24

• Manufacturer Part Number: LTC1196-1BC
• Description: 8-Bit/ SO-8/ 1MSPS ADCs with Auto-Shutdown Options
• Manufacturer: Linear Technology

LTC1196/LTC1198
Interfacing the LTC1198 to the TMS320C25 DSP
Figure 15 illustrates the interface between the LTC1198
8-bit data acquisition system and the TMS320C25 digital
signal processor (DSP). The interface, which is optimized
for speed of transfer and minimum processor supervi-
sion, can complete a conversion and shift the data in 4 s
with f
is limited by maximum clock frequency of the serial port
of the TMS320C25 which is 5MHz. The supply voltage for
24
TYPICAL
Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP
CLK
TMS320C25
= 5MHz. The cycle time, 4 s, of each conversion
CLKX
CLKR
A
FSR
FSX
DX
DR
PPLICATI
DATA
CLK
CS
B7
B6
B5
B4
B3
B2
B1
B0
5MHz CLK
70
O
140 210 280
U
CS
D
D
CLK
IN
OUT
S
LTC1198
1196/98 F15
CH0
CH1
Figure 14. The Timing Diagram
350
420
490
560
TIME (ns)
the LTC1198 in Figure 15 can be 2.7V to 6V with f
5MHz. At 2.7V, f
Recommended Operating Conditions for limits over tem-
perature.
Hardware Description
The circuit works as follows: the LTC1198 clock line
controls the A/D conversion rate and the data shift rate.
Data is transferred in a synchronous format over D
D
that of the LTC1198. The data shift clock lines (CLKR,
CLKX) are inputs only. The data shift clock comes from an
external source. Inverting the shift clock is necessary
because the LTC1198 and the TMS320C25 clock the input
data on opposite edges.
The schematic of Figure 15 is fed by an external clock
source. The signal is fed into the CLK pin of the LTC1198
directly. The signal is inverted with a 74HC04 and then
applied to the data shift clock lines (CLKR, CLKX). The
framing pulse of the TMS320C25 is fed directly to the CS
of the LTC1198. DX and DR are tied directly to D
D
630
OUT
OUT
. The serial port of the TMS320C25 is compatible with
700 770
respectively.
840 910
CLK
980 1050 1120
= 5MHz will work at 25 C. See
1196/98 F14
IN
IN
CLK
and
and
=