LTC1402 Linear Technology, LTC1402 Datasheet - Page 17

• Manufacturer Part Number: LTC1402
• Description: Serial 12-Bit/ 2.2Msps Sampling ADC with Shutdown
• Manufacturer: Linear Technology

HARDWARE INTERFACE TO TMS320C54x
The LTC1402 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 13 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 2.2Msps conversion rate of the LTC1402.
The DSP assembly code sets frame sync mode at the BFSR
pin to accept an external positive going pulse, and the
serial clock at the BCLKR pin to accept an external positive
; ***************************************************************************
; Files: BSP2KB.ASM ->
; 2kbyte collection into DSKPlus TMS320C542 with Serial Port interface to LTC1402
; first element at 1024, last element at 1023, two middle elements at 2047 and 0000
; bipolar mode
; ***************************************************************************
start:
sinepeek:
wait goto wait
APPLICATIONS
.text
tim=#0fh
prd=#0fh
tcr = #10h
tspc = #0h
pmst = #01a0h ; set up iptr. Processor Mode STatus register
sp = #0700h
dp = #0
ar2 = #1800h
ar3 = #0800h
ar4 = #0h
call sineinit
call sineinit
.mmregs
.setsect “vectors”, 0x180,0
.width
.length 110
.title “sineb0 BSP in auto buffer mode”
.setsect “.text”,
.setsect “buffer”, 0x800,0
.setsect “result”, 0x1800,0
160
;Make sure /PWRDWN is low at J1-9 to turn off AC01 adc
; stop timer
; stop TDM serial port to AC01
; init stack pointer.
; data page
; pointer to computed receive buffer.
; pointer to Buffered Serial Port receive buffer
; reset record counter
; Double clutch the initialization to insure a proper
; insert debugger break here to view results
; reset. The external frame sync must occur 2.5 clocks
; or more after the port comes out of reset.
0x500,0
U
LTC1402
INFORMATION
U
OGND
CONV
OV
D
SCK
OUT
;Set address of executable
;Set address of incoming 1402 data
;Set address of BSP buffer for clearing
;Set address of result for clearing
;.text marks start of code
DD
11
16
15
10
9
W
CONV
CLK
Figure 13. DSP Serial Interface to TMS320C54x
U
INTERFACE LINK
3-WIRE SERIAL
edge clock. Buffers near the LTC1402 may be added to
drive long tracks to the DSP to prevent corruption of the
signal to LTC1402. This configuration is adequate to
traverse a typical system board, but source resistors at the
buffer outputs, and termination resistors at the DSP may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the D
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 2.5V swing of the terminated transmission
lines. The OV
driven directly from the DSP.
5V
REF
DD
supply output driver supply voltage can be
B11
B10
V
BFSR
BCLKR
BDR
TMS320C54x
CC
1402 F13
LTC1402
17
OUT