LTC1416 Linear Technology, LTC1416 Datasheet - Page 6

• Manufacturer Part Number: LTC1416
• Description: Low Power 14-Bit/ 400ksps Sampling ADC
• Manufacturer: Linear Technology

PI FU CTIO S
FU CTIO AL BLOCK DIAGRA
LTC1416
A
A
V
with 1 F.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 22 F tantalum in parallel with 0.1 F
ceramic, or 22 F ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
6
IN
IN
REF
U
+
–
U
(Pin 2):
(Pin 1): 2.5V Positive Analog Input.
(Pin 3): 2.5V Reference Output. Bypass to AGND
REFCOMP
U
(4.06V)
DGND
AGND
V
A
A
REF
IN
IN
U
+
–
2.5V Negative Analog Input.
U
4k
REF AMP
2.5V REF
INTERNAL
CLOCK
W
SHDN
14-BIT CAPACITIVE DAC
SUCCESSIVE APPROXIMATION
C
C
CONVST
CONTROL LOGIC
SAMPLE
SAMPLE
REGISTER
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
is valid on the rising edge of BUSY.
V
with 10 F tantalum in parallel with 0.1 F ceramic, or
10 F ceramic.
DV
AV
with 10 F tantalum in parallel with 0.1 F ceramic, or
10 F ceramic.
SS
RD
DD
DD
(Pin 26): – 5V Negative Supply. Bypass to AGND
(Pin 27): 5V Positive Supply. Tie to Pin 28.
(Pin 28): 5V Positive Supply. Bypass to AGND
CS
BUSY
14
ZEROING SWITCHES
+
–
COMP
OUTPUT LATCHES
•
•
•
D13
D0
AV
DV
V
1416 BD
SS
DD
DD