LTC1748 Linear Technology, LTC1748 Datasheet - Page 11

• Manufacturer Part Number: LTC1748
• Description: 14-Bit 80Msps Low Noise ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
SENSE
4.7 F
A
A
V
IN
IN
CM
+
–
INPUT
REFERENCE
S/H
SELECT
RANGE
2.35V
U
REF
BUF
U
FIRST PIPELINED
ADC STAGE
(5 BITS)
W
DIFF
AMP
REF
0.1 F
1 F
REFLB
Figure 1. Functional Block Diagram
REFL
REFHA
U
4.7 F
SECOND PIPELINED
REFH
ADC STAGE
(4 BITS)
REFLA REFHB
1 F
0.1 F
INTERNAL CLOCK SIGNALS
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
CONVERTER OPERATION
The LTC1748 is a CMOS pipelined multistep converter.
The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
see the Timing Diagram section. The analog input is
differential for improved common mode noise immunity
and to maximize the input range. Additionally, the differen-
tial input drive will reduce even order harmonics of the
sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1748 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
DIFFERENTIAL
LOW JITTER
DRIVER
CLOCK
INPUT
ENC
SNR
ENC
JITTER
THIRD PIPELINED
ADC STAGE
= –20log (2 ) • F
CALIBRATION LOGIC
(4 BITS)
CONTROL LOGIC
MSBINV
AND
OE
IN
FOURTH PIPELINED
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• T
AND CORRECTION
SHIFT REGISTER
ADC STAGE
DRIVERS
JITTER
(4 BITS)
OUTPUT
OGND
LTC1748
1748 F01
OV
OF
D13
D0
CLKOUT
11
DD
0.5V TO
5V
1748fa