LTC1748 Linear Technology, LTC1748 Datasheet - Page 15

• Manufacturer Part Number: LTC1748
• Description: 14-Bit 80Msps Low Noise ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
3. If the ADC is clocked with a sinusoidal signal, filter the
4. Balance the capacitance and series resistance at both
coupled use a higher turns ratio to increase the
amplitude.
encode signal to reduce wideband noise.
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
V
THRESHOLD
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
CLOCK
INPUT
U
= 2V
0.1 F
0.1 F
U
ANALOG INPUT
50
2V
ENC
ENC
W
1:4
LTC1748
1748 F08a
Figure 7. Transformer Driven ENC/ENC
ENC
ENC
U
LTC1748
V
V
DD
DD
2V BIAS
2V BIAS
6k
6k
5V
The encode inputs have a common mode range of 1.8V to
V
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1748 is 80Msps. For
the ADC to operate properly the encode signal should have
a 50% ( 4%) duty cycle. Each half cycle must have at least
6ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
DD
. Each input may be driven from ground to V
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
MC100LVELT22
BIAS
D0
3.3V
Q0
Q0
TO INTERNAL
ADC CIRCUITS
130
83
3.3V
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1748 F07
130
83
ENC
ENC
LTC1748
LTC1748
1748 F08b
15
DD
1748fa
for