LTC2173-14 Linear Technology Corporation, LTC2173-14 Datasheet - Page 23

• Manufacturer Part Number: LTC2173-14
• Description: (LTC217x-14) 125Msps Low Power Quad ADCs
• Manufacturer: Linear Technology Corporation

www.DataSheet4U.com
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
The digital outputs of the LTC2175-14/LTC2174-14/
LTC2173-14 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode). At lower sampling
rates there is a one bit per channel option (1-lane mode).
The data can be serialized with 16, 14, or 12-bit serializa-
tion (see timing diagrams for details). Note that with 12-bit
serialization the two LSBs are not available—this mode
is included for compatibility with the 12-bit versions of
these parts.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for all
serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2175-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2174-14) or 80MHz (LTC2173-14).
SERIALIZATION MODE
2-Lane
2-Lane
2-Lane
1-Lane
1-Lane
1-Lane
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
MAXIMUM SAMPLING
FREQUENCY , f
62.5
71.4
83.3
125
125
125
S
(MHz)
DCO FREQUENCY
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by control register A2 in the serial pro-
gramming mode. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the
parallel programming mode the SCK pin can select either
3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any refl ections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
In the parallel programming mode the SDO pin enables
internal termination.
3.5 • f
4 • f
3 • f
8 • f
7 • f
6 • f
S
S
S
S
S
S
LTC2174-14/LTC2173-14
FR FREQUENCY
0.5 • f
f
f
f
f
f
S
S
S
S
S
S
LTC2175-14/
DD
and OGND which are
SERIAL DATA RATE
16 • f
14 • f
12 • f
8 • f
7 • f
6 • f
S
S
S
S
S
S
23
21754314p