LTC2173-14 Linear Technology Corporation, LTC2173-14 Datasheet - Page 27

• Manufacturer Part Number: LTC2173-14
• Description: (LTC217x-14) 125Msps Low Power Quad ADCs
• Manufacturer: Linear Technology Corporation

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APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
Bit 5
Bits 4-0
Bits 7-5
Bit 4
Bit 3
Bits 2-0
Bit 7
Bit 6
Bit 5-0
Bit 7-0
OUTTEST
ILVDS2
TP7
D7
D7
D7
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
SLEEP: NAP_4:NAP_1
00000 = Normal Operation
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 2 in Nap Mode
0X1XX = Channel 3 in Nap Mode
01XXX = Channel 4 in Nap Mode
1XXXX = Sleep Mode. All Channels are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
TERMON
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0
OUTOFF
0 = Digital Outputs are Enabled.
1 = Digital Outputs are Disabled.
OUTMODE2:OUTMODE0
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
OUTTEST
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Unused, Don’t Care Bit.
TP13:TP8
TP13:TP8 Set the Test Pattern for Data Bit 13(MSB) Through Data Bit 8.
TP7:TP0
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0(LSB).
ILVDS1
TP6
D6
D6
D6
X
Output Disable Bit
LVDS Internal Termination Bit
Digital Output Test Pattern Control Bit
Test Pattern Data Bits (MSB)
Test Pattern Data Bits (LSB)
Two’s Complement Mode Control Bit
ILVDS0
Sleep/Nap Mode Control Bits
TP13
TP5
D5
D5
D5
Digital Output Mode Control Bits
TERMON
TP12
TP4
D4
D4
D4
OUTOFF
TP11
TP3
D3
D3
D3
LTC2174-14/LTC2173-14
OUTMODE2
TP10
TP2
D2
D2
D2
OUTMODE1
LTC2175-14/
TP9
TP1
D1
D1
D1
OUTMODE0
TP8
TP0
D0
D0
D0
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