LTC2173-14 Linear Technology Corporation, LTC2173-14 Datasheet - Page 25

• Manufacturer Part Number: LTC2173-14
• Description: (LTC217x-14) 125Msps Low Power Quad ADCs
• Manufacturer: Linear Technology Corporation

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APPLICATIONS INFORMATION
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50μs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2175-14/LTC2174-14/
LTC2173-14 can be programmed by either a parallel inter-
face or a simple serial interface. The serial interface has
more fl exibility and can program all available modes. The
parallel interface is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V
logic inputs that set certain operating modes. These pins
can be tied to V
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
DD
. The CS, SCK, SDI and SDO pins are binary
DD
or ground, or driven by 1.8V, 2.5V, or
Table 3. Parallel Programming Mode Control Bits (PAR/SER = V
Pin
CS
SCK
SDI
SDO
DESCRIPTION
2-Lane / 1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the fi rst 16 rising edges of SCK.
Any SCK rising edges after the fi rst 16 are ignored. The
data transfer ends when CS is taken high again.
The fi rst bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The fi nal eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams sections). During a read back command the
register is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back through
SDO, an external 2k pull-up resistor is required. If serial
LTC2174-14/LTC2173-14
DD
)
LTC2175-14/
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21754314p