LTC2309 Linear Technology Corporation, LTC2309 Datasheet - Page 9

no-image

LTC2309

Manufacturer Part Number
LTC2309
Description
12-Bit SAR ADC
Manufacturer
Linear Technology Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC2309CF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC2309CF#PBF
Manufacturer:
LT
Quantity:
1 000
Part Number:
LTC2309CF#PBF
Manufacturer:
LT凌特厂
Quantity:
20 000
Part Number:
LTC2309CUF
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC2309CUF#PBF
Manufacturer:
LT
Quantity:
3 276
Part Number:
LTC2309CUF#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC2309HF#PBF
Manufacturer:
LT
Quantity:
1 603
Part Number:
LTC2309IF#PBF
Manufacturer:
LT
Quantity:
3 276
Part Number:
LTC2309IF#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC2309IUF#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
www.DataSheet4U.com
APPLICATIONS INFORMATION
Overview
The LTC2309 is a low noise, 8-channel, 12-bit succes-
sive approximation register (SAR) A/D converter with an
I
precision internal reference and a confi gurable 8-chan-
nel analog input multiplexer (MUX). The ADC may be
confi gured to accept single-ended or differential signals
and can operate in either unipolar or bipolar mode. A
sleep mode option is also provided to further reduce
power during inactive periods.
The LTC2309 communicates through a 2-wire I
compatible serial interface. Conversions are initiated
by signaling a Stop condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge (NAK) an external request
until the conversion is fi nished. After a conversion is
fi nished, the device is ready to accept a read/write
request. Once the LTC2309 is addressed for a read
operation, the device begins outputting the conversion
result under the control of the serial clock (SCL). There
is no latency in the conversion result. There are 12
bits of output data followed by 4 trailing zeros. Data is
updated on the falling edges of SCL, allowing the user
to reliably latch data on the rising edge of SCL. A write
operation may follow the read operation by using a
Repeat Start or a Stop condition may be given to start
a new conversion. By selecting a write operation, the
ADC can be programmed with a 6-bit D
D
modes of operation of the ADC.
During a conversion, the internal 12-bit capacitive
charge redistribution DAC output is sequenced through
a successive approximation algorithm by the SAR start-
ing from the most signifi cant bit (MSB) to the least
signifi cant bit (LSB). The sampled input is successively
compared with binary weighted charges supplied by
the capacitive DAC using a differential comparator. At
the end of a conversion, the DAC output balances the
analog input. The SAR contents (a 12-bit data word)
that represent the sampled analog input are loaded into
12 output latches that allow the data to be shifted out
via the I
2
IN
C compatible serial interface. The LTC2309 includes a
word confi gures the MUX and programs various
2
C interface.
IN
word. The
2
C
Programming the LTC2309
The various modes of operation of the LTC2309 are
programmed by a 6-bit D
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the fi rst rising edge
and the SLP bit on the sixth rising edge (see Figure 8b
in the I
defi ned as follows:
Analog Input Multiplexer
The analog input MUX is programmed by the S/D,
O/S, S1 and S0 bits of the D
MUX confi gurations for all combinations of the con-
fi guration bits. Figure 1a shows several possible MUX
confi gurations and Figure 1b shows how the MUX can
be reconfi gured from one conversion to the next.
Driving the Analog Inputs
The analog inputs of the LTC2309 are easy to drive.
Each of the analog inputs can be used as a single-ended
input relative to the COM pin (CH0-COM, CH1-COM,
etc.) or in differential input pairs (CH0 and CH1, CH2
and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows
how to drive COM for single-ended inputs in unipolar
and bipolar modes. Regardless of the MUX confi gura-
tion, the “+” and “–“ inputs are sampled at the same
instant. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection
of the sample-and-hold circuit. The inputs draw only
one small current spike while charging the sample-and-
hold capacitors during the acquire mode. In conversion
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
S1 = CHANNEL SELECT BIT 1
S0 = CHANNEL SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
S/D O/S S1
2
C Interface section). The input data word is
S0 UNI SLP
IN
word. The SDI input data
IN
word. Table 1 lists the
LTC2309
9
2309f

Related parts for LTC2309