LTC2366 Linear Technology, LTC2366 Datasheet - Page 14

• Manufacturer Part Number: LTC2366
• Description: (LTC2365 / LTC2366) 12-Bit Serial Sampling ADCs
• Manufacturer: Linear Technology

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LTC2365/LTC2366
APPLICATIONS INFORMATION
OVERVIEW
The LTC2365/LTC2366 use a successive approximation
algorithm and internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output. Both devices operate
from a single 2.35V to 3.6V supply. The LTC2366 samples
at a rate of 3Msps with a 48MHz clock while the LTC2365
samples at a rate of 1Msps with a 16MHz clock.
The LTC2365/LTC2366 contain a 12-bit, switched-capacitor
ADC, a sample-and-hold, and a serial interface (see Block
Diagram) and are available in tiny 6- and 8-lead TSOT-23
packages. The devices provide sleep mode control through
the serial interface to save power during inactive periods
(see the SLEEP MODE section).
The S6 package of the LTC2365/LTC2366 uses V
reference and has an analog input range of 0V to V
ADC samples the analog input with respect to GND and
outputs the result through the serial interface.
The TS8 package provides two additional pins: a reference
input pin, V
can operate with reduced spans down to 1.4V and achieve
342μV resolution. OV
digital output pin, SDO, and allows the device to com-
municate with 1.8V, 2.5V or 3V digital systems.
SERIAL INTERFACE
The LTC2365/LTC2366 communicate with microcontrollers,
DSPs and other external circuitry via a 3-wire interface.
Figure 10 shows the serial interface timing diagram, while
14
SDO
SCK
CS
REF
, and an output supply pin, OV
ZERO
t
2
t
3
1
ZERO
DD
controls the output swing of the
2
(MSB)
B11
Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram
3
B10
t
CONV
4
13t
B9
SCK
t
t
6
4
DD
5
. The ADC
DD
DD
as the
. The
t
B1
7
13
t
THROUGHPUT
Figures 11 and 12 detail the timing diagrams of conversion
cycles in 14 and 16 SCK cycles respectively.
Data Transfer
A falling CS edge starts a conversion and frames the se-
rial data transfer. SCK provides the conversion clock and
controls the data transfer during the conversion.
CS going low clocks out the fi rst leading zero and sub-
sequent SCK falling edges clock out the remaining data,
beginning with the second leading zero. (Therefore, the
fi rst SCK falling edge captures the fi rst leading zero and
clocks out the second leading zero). The timing diagram
in Figure 12 shows that the fi nal bit in the data transfer is
valid on the 16th falling edge, since it is clocked out on
the previous 15th falling edge.
In applications with a slower SCK, it is possible to capture
data on each SCK rising edge. In such cases, the fi rst fall-
ing edge of SCK clocks out the second leading zero and
can be captured on the fi rst rising edge. However, the fi rst
leading zero clocked out when CS goes low is missed as
shown in Figures 11 and 12. In Figure 12, the 15th falling
edge of SCK clocks out the last bit and can be captured
on the 15th rising SCK edge.
If CS goes low while SCK is low, then CS clocks out the
fi rst leading zero and can be captured on the SCK rising
edge. The next SCK falling edge clocks out the second
leading zero and can be captured on the following rising
edge as shown in in Figure 10.
B0
14
t
5
ZERO
15
ZERO
16
t
8
t
ACQ
Hi-Z STATE
t
QUIET
t
1
23656 F10
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