LTC2366 Linear Technology, LTC2366 Datasheet - Page 15

• Manufacturer Part Number: LTC2366
• Description: (LTC2365 / LTC2366) 12-Bit Serial Sampling ADCs
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Achieving 3Msps Sample Rate with LTC2366
CS going low places the sample-and-hold into hold mode
and starts a conversion. The LTC2365/LTC2366 require
at least 14 SCK cycles to fi nish the conversion. The
conversion terminates after the 13th falling SCK edge,
which clocks out B0. The 14th falling SCK edge places
the sample-and-hold back into sample mode.
Ignoring the last two trailing zeros, the user can bring CS
high after the 14th falling SCK edge. The user can also
keep the last two trailing zeros by bringing CS high right
after the 16th falling SCK. In both cases, a sample rate
of 3Msps can be achieved by using a 48MHz SCK clock
on the LTC2366, where t
SDO
SCK
CS
SDO
SCK
CS
t
2
Z
Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles
Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles
THROUGHPUT
1
t
3
ZERO
t
2
Z
1
t
3
ZERO
2
(MSB)
B11
2
(MSB)
is 333ns.
B11
3
B10
t
CONV
3
B10
4
t
CONV
B9
t
t
6
4
4
5
B9
t
t
6
4
t
THROUGHPUT
5
t
7
t
THROUGHPUT
t
B1
7
Serial Data Output (SDO)
The SDO output remains in the high impedance state while
CS is high. The falling edge of CS starts the conversion
and enables SDO. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB fi rst.
The data stream consists of two leading zeros followed
by 12 bits of conversion data and two trailing zeros. The
SDO output returns to the high impedance state at the
16th falling edge of SCK or sooner by bringing ⎯ C ⎯ S high
before the 16th falling edge of SCK.
The output swing on the SDO pin is controlled by the V
pin voltage in the S6 package and by the OV
in the TS8 package.
13
B1
B0
13
t
5
14
t
B0
5
ZERO
14
15
t
9
ZERO
LTC2365/LTC2366
Hi-Z STATE
16
t
ACQ
t
t
QUIET
1
t
t
8
ACQ
OR t
9
Hi-Z STATE
t
QUIET
t
1
23656 F11
23656 F12
DD
pin voltage
15
23656f
DD