LTC2424 Linear Technology, LTC2424 Datasheet - Page 19

• Manufacturer Part Number: LTC2424
• Description: 4-/8-Channel 20-Bit uPower No Latency ADCs
• Manufacturer: Linear Technology

APPLICATIONS
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t
falling edge of CSADC (if EOC = 0) or t
goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t
internal oscillator (F
by an external oscillator of frequency f
3.6/f
device remains in the sleep state. The conversion result is
held in the internal static shift register.
If CSADC remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
EOSC
SCKCLK
CSMUX
CSADC
SDO
D
IN
. If CSADC is pulled HIGH before time t
TEST EOC
t
EOCtest
DON’T CARE
U
EOCtest
0
Hi-Z
= logic LOW or HIGH). If F
INFORMATION
U
TEST EOC
is 23 s if the device is using its
Hi-Z
W
EOCtest
EOSC
Figure 16. Internal Serial Clock Timing Diagram
BIT23
EOCtest
EOCtest
, then t
, the first rising
BIT22
TO 1.12V
–0.12V
BIT21
EOCtest
U
O
SIG
after EOC
TO V
after the
2.7V TO 5.5V
is driven
EOCtest
0.1V
REF
REF
BIT20
CC
EXR
, the
BIT19 BIT18
MSB
is
V
FS
CH0
TO CH7
MUXOUT
ADCIN
ZS
GND
LTC2424/LTC2428
CC
SET
SET
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D
edge of CLK. As shown in Figure 16, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D
output state, the previous channel selection remains valid.
IN
CSMUX
CSADC
SDO
pin on the rising edge of CLK. The first bit is an enable
SCK
CLK
D
BIT4 BIT3 BIT2 BIT1
F
IN
O
EN
IN
is latched into the multiplexer on the rising
D2
V
CC
D1
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
CS
LSB
BIT0
D0
LTC2424/LTC2428
10k
IN
is held LOW during the data
Hi-Z
DON’T CARE
TEST EOC
24248 F16
19