LTC2424 Linear Technology, LTC2424 Datasheet - Page 7

• Manufacturer Part Number: LTC2424
• Description: 4-/8-Channel 20-Bit uPower No Latency ADCs
• Manufacturer: Linear Technology

FU CTIO AL BLOCK DIAGRA
APPLICATIONS
TEST CIRCUITS
Converter Operation Cycle
The LTC2424/LTC2428 are low power, 4-/8-channel delta-
sigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selection may be performed while the device is in the sleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input
FS
ZS
GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
SET
SET
CC
U
U
SDO
U
INFORMATION
Hi-Z TO V
V
V
3.4k
U
OL
OH
TO V
TO Hi-Z
DAC
OH
OH
W
C
LOAD
24248 TC01
= 20pF
U
W
(D
interface requires only four wires.
Initially, the LTC2424 or LTC2428 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Channel selection for the next conversion cycle is per-
formed while the device is in the sleep state or at the end
IN
). By tying SCK to CLK and CSADC to CSMUX, the
ADC
SDO
Hi-Z TO V
V
V
OH
OL
V
AUTOCALIBRATION
TO Hi-Z
TO V
CC
DECIMATING FIR
AND CONTROL
3.4k
C
OL
OL
LTC2424/LTC2428
LOAD
24248 TC02
= 20pF
OSCILLATOR
INTERFACE
INTERNAL
CHANNEL
SELECT
SERIAL
24248 BD
(INT/EXT)
F
SDO
SCK
CSADC
CSMUX
D
CLK
O
IN
7