LTC3642 Linear Technology, LTC3642 Datasheet - Page 14

• Manufacturer Part Number: LTC3642
• Description: High Voltage 50mA Synchronous Step-Down Converter
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC3642
To increase the duration of the reference voltage soft-start,
place a capacitor from the SS pin to ground. An internal
5μA pull-up current will charge this capacitor, resulting in
a soft-start ramp time given by:
When the LTC3642 detects a fault condition (input supply
undervoltage or overvoltage) or when the RUN pin falls
below 1.1V, the SS pin is quickly pulled to ground and the
internal soft-start timer is reset. This ensures an orderly
restart when using an external soft-start capacitor.
The duration of the 1ms internal peak current soft-start
may be increased by placing a capacitor from the I
to ground. The peak current soft-start will ramp from 25mA
to the fi nal peak current value determined by a resistor
from I
I
and ground, the peak current ramps linearly from 25mA
to 115mA, and the peak current soft-start time can be
expressed as:
A linear ramp of peak current appears as a quadratic
waveform on the output voltage. For the case where the
peak current is reduced by placing a resistor from I
to ground, the peak current offset ramps as a decaying
exponential with a time constant of R
case, the peak current soft-start time is approximately
3 • R
Unlike the SS pin, the I
ground during an abnormal event; however, if the I
pin is fl oating (programmed to 115mA peak current),
the SS and I
to a capacitor to ground. For this special case, both the
peak current and the reference voltage will soft-start on
power-up and after fault conditions. The ramp time for
this combination is C
14
SET
t
t
SS
SS ISET
pin. With only a capacitor connected between I
ISET
SET
(
=
C
• C
to ground. A 1μA current is sourced out of the
SS
)
SET
=
ISET
•
C
. 0 8
5
ISET
.
pins may be tied together and connected
μA
V
•
SS(ISET)
0 8
1
.
μA
SET
V
pin does not get pulled to
• (0.8V/6μA).
ISET
• C
ISET
. For this
SET
SET
pin
SET
SET
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the effi ciency and which change would produce
the most improvement. Effi ciency can be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
operating current dominates the effi ciency loss at very
low load currents whereas the I
effi ciency loss at medium to high load currents.
1. The V
2. I
Effi ciency = 100% – (L1 + L2 + L3 + ...)
The DC supply current as given in the electrical charac-
teristics and the internal MOSFET gate charge currents.
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge, dQ, moves from V
ground. The resulting dQ/dt is the current out of V
that is typically larger than the DC bias current.
internal switches, R
switching, the average output current fl owing through
the inductor is “chopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
of the top and bottom switch R
duty cycle (DC = V
The R
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain the I
R
average output current:
2
SW
R losses are calculated from the resistances of the
R
I
2
SW
R Loss = I
to R
IN
DS(ON)
= (R
operating current comprises two components:
L
IN
and multiply the result by the square of the
DS(ON)TOP
operating current and I
for both the top and bottom MOSFETs can
O
2
(R
OUT
SW
SW
)DC + (R
, and external inductor R
/V
+ R
IN
) as follows:
L
)
DS(ON)BOT
2
R loss dominates the
DS(ON)
2
R losses, simply add
2
R losses. The V
values and the
)(1 – DC)
L
. When
IN
3642f
to
IN
IN