LTC4100 Linear Technology, LTC4100 Datasheet - Page 17

• Manufacturer Part Number: LTC4100
• Description: Smart Battery Charger Controller
• Manufacturer: Linear Technology

The Current DAC Block
The current DAC is a delta-sigma modulator which con-
trols the effective value of an external resistor, R
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the ChargingCurrent() value,
received via the SMBus, to a variable resistance equal to:
Therefore, programmed current is equal to:
When a value less than 1/16th of the maximum current
allowed by I
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is I
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/bit,
so that the charger has time to settle to the I
The resulting average charging current is equal to that
requested by the ChargingCurrent() value.
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
OPERATIO
NOTE: THE LTC4100 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.184V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
(102.3mV/R
for ChargingCurrent() < I
1.25R
SET
Figure 6. Transfer Function of Charger
LIM
/ChargingCurrent()/I
25
20
15
10
5
0
0
SENSE
MAX
R
is applied to the current DAC input, the
VLIM
U
5
/8. The delta-sigma output gates this
= 33k
) (ChargingCurrent()/I
PROGRAMMED VALUE (V)
10
15
LIM[x]
20
LIM[x]
25
.
30
)
4100 F06
35
LIM
MAX
[x]),
SET
/8 value.
, used
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, inde-
pendent of the I
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than V
130mV higher than V
CHGEN pin is forced low unless this condition is met. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
I
LIMIT
Figure 8. Charging Current Waveform in Low Current Mode
0
/8
~40ms
Figure 7. Current DAC Operation
(FROM CA1 AMP)
LIM
I
DC
R
SET
I
PROG
setting.
V
CLP
REF
MODULATOR
to activate the charger. The
–
+
AVERAGE CHARGER CURRENT
-
CLP
CHARGING_CURRENT
VALUE
, it must go at least
I
TH
LTC4100
4100 F07
sn4100 4100is
17
4100 F08