LTC4100 Linear Technology, LTC4100 Datasheet - Page 8

• Manufacturer Part Number: LTC4100
• Description: Smart Battery Charger Controller
• Manufacturer: Linear Technology

LTC4100
OPERATIO
Overview (Refer to Block Diagram)
The LTC4100 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger cur-
rent, an 11-bit DAC to control charger voltage, a SafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled
if DCDIV is low, or the SafetySignal is decoded as
RES_HOT. If a battery is inserted and AC power is con-
nected, the battery will be charged with an 80mA “wake-
up” current. The wake-up current is discontinued after
t
RES_C0LD, and the battery or host doesn’t transmit
charging commands.
The SMBus interface and control block receives
ChargingCurrent() and ChargingVoltage() commands via
the SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a t
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence.
ChargingCurrent() and ChargingVoltage() values are com-
pared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The charger controller will assert SMBALERT whenever a
status change is detected, namely: AC_PRESENT,
BATTERY_PRESENT, ALARM_INHIBITED, or V
power-fail. The host may query the charger, via the
SMBus, to obtain ChargerStatus() information. SMBALERT
will be deasserted upon a successful read of
ChargerStatus() or a successful Alert Response
Address (ARA) request.
Battery Charger Controller
The LTC4100 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator I
the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current
8
TIMEOUT
if the SafetySignal is decoded as RES_UR or
U
CMP
resets the SR latch. While
TIMEOUT
interval, the
DD
The peak inductor current, at which I
latch, is controlled by the voltage on I
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the I
I
The voltage at BAT is divided down by an internal resistor
divider set by the V
decrease I
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
R
voltage to reduce charging current.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that "load dump" themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
comparator I
The oscillator uses the equation,
to set the bottom MOSFET on time. The result is quasi-
constant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
TH
TGATE
CL
BGATE
INDUCTOR
CURRENT
t
for the desired voltage across R
). At input current limit, CL1 will decrease the I
OFF
OFF
OFF
ON
ON
(
TH
V
(
V
DCIN
DCIN
REV
if the divider voltage is above the 1.19V
, or the beginning of the next cycle.
–
•
V
f
OSC
DAC
BAT
)
Figure 3.
and is used by error amp EA to
)
t
OFF
DAC
at the I
SENSE
TRIP POINT SET
BY I
CMP
DC
TH
TH
.
pin and adjusts
. I
VOLTAGE
resets the SR
TH
is in turn
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TH