74HCT574D,653 NXP Semiconductors, 74HCT574D,653 Datasheet - Page 9

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74HCT574D,653

Manufacturer Part Number
74HCT574D,653
Description
IC FLIP FLOP OCTAL D 3ST 20SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Type
D-Type Busr
Datasheet

Specifications of 74HCT574D,653

Output Type
Tri-State Non Inverted
Package / Case
20-SOIC (7.5mm Width)
Function
Standard
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
69MHz
Delay Time - Propagation
18ns
Trigger Type
Positive Edge
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
8
Logic Family
74HCT
Logic Type
D-Type Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
15 ns
High Level Output Current
- 6 mA
Low Level Output Current
6 mA
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
4.5 V
Technology
CMOS
Number Of Bits
8
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
5V
Package Type
SO
Frequency (max)
20MHz
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1557-2
74HCT574D-T
933715630653
NXP Semiconductors
11. Waveforms
74HC_HCT574
Product data sheet
Fig 7.
Fig 8.
Measurement points are given in
V
Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
Measurement points are given in
V
The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
OL
OL
and V
and V
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
Qn output
CP input
Dn input
Qn output
CP input
GND
GND
V
GND
Table
V
Table
V
V
OH
OL
V
V
OH
OL
All information provided in this document is subject to legal disclaimers.
V
I
I
I
8.
8.
Rev. 3 — 15 December 2010
V
M
V
90 %
M
t
PHL
t
V
W
t
M
su
1/f
V
M
10 %
t
max
Octal D-type flip-flop; positive edge-trigger; 3-state
h
t
THL
V
M
74HC574; 74HCT574
t
PLH
t
su
001aan292
t
t
h
TLH
mna803
© NXP B.V. 2010. All rights reserved.
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