SC16IS762 Philips Semiconductors, SC16IS762 Datasheet - Page 14

• Manufacturer Part Number: SC16IS762
• Description: (SC16IS752 / SC16IS762) Dual UART
• Manufacturer: Philips Semiconductors

NXP Semiconductors
SC16IS752_SC16IS762_6
Product data sheet
7.5 Interrupts
The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized
levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable
each of the seven types of interrupts and the IRQ signal in response to an interrupt
generation. When an interrupt is generated, the IIR indicates that an interrupt is pending
and provides the type of interrupt through IIR[5:0].
control functions.
Table 6.
It is important to note that for the framing error, parity error, and break conditions, Line
Status Register bit 7 (LSR[7]) generates the interrupt. LSR[7] is set when there is an error
anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in
the FIFO. LSR[4:2] always represent the error status for the received character at the top
of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
IIR[5:0]
00 0001
00 0110
00 1100
00 0100
00 0010
00 0000
00 1110
01 0000
10 0000
Summary of interrupt control functions
Priority
level
none
1
2
2
3
4
5
6
7
Interrupt type
none
receiver line status
RX time-out
RHR interrupt
THR interrupt
modem status
I/O pins
Xoff interrupt
CTS, RTS
Rev. 06 — 19 December 2006
Dual UART with I
2
SC16IS752/SC16IS762
Interrupt source
none
Overrun Error (OE), Framing Error (FE), Parity Error
(PE), or Break Interrupt (BI) errors occur in
characters in the RX FIFO
stale data in RX FIFO
receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
change of state of modem input pins
input pins change of state
receive Xoff character(s)/special character
RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 6
summarizes the interrupt
© NXP B.V. 2006. All rights reserved.
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