MX28F2000P Macronix International, MX28F2000P Datasheet
MX28F2000P
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MX28F2000P Summary of contents
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... Four 4-KB blocks (Top) – Fourteen 16-KB blocks – Four 4-KB blocks (Bottom) GENERAL DESCRIPTION The MX28F2000P is a 2-mega bit Flash memory or- ganized as 256K bytes of 8 bits each. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX28F2000P is packaged in 32-pin PDIP, PLCC and TSOP ...
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... MX28F2000P Block Address and Block Structure ...
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... MX28F2000P (NORMAL TYPE MX28F2000P (REVERSE TYPE) PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Write enable Pin Program Supply Voltage Power Supply Pin (+5V) Ground Pin REV ...
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... BLOCK DIAGRAM CE CONTROL OE INPUT WE LOGIC ADDRESS LATCH A0-A17 AND BUFFER Q0-Q7 P/N: PM0380 MX28F2000P PROGRAM/ERASE HIGH VOLTAGE MX28F2000P FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 MODE LOGIC STATE REGISTER COMMAND DATA DECODER COMMAND DATA LATCH REV. 1.5, OCT 29, 1998 ...
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... During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplifica- tion, the MX28F2000P is designed to support either controlled writes. During a system write cycle, addresses are latched on the falling edge whichever occurs last ...
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... Write X 00H Write X 90H Write X 30H Write X 20H Write X 40H Write X 20H Write X 60H Write EVA A0H Write X FFH 6 MX28F2000P SECOND BUS CYCLE OPERATION ADDRESS DATA Read IA ID Write X 30H Write EA D0H Write PA PD Write X 20H Write EA 60H Read X EVD Write X FFH REV ...
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... Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Ta- ble 1 defines these MX28F2000P register commands. Table 2 defines the bus operations of MX28F2000P. TABLE 2. MX28F2000P BUS OPERATIONS OPERATION READ-ONLY Read ...
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... This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hard-wired to the MX28F2000P, the device powers up and remains enabled for reads until the command register contents are changed. SILICON-ID-READ COMMAND Flash-memories are intended for use in applications where the local CPU alters memory contents ...
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... A valid command must then be written to place the device in the desired state. WRITE OPERATON STATUS TOGGLE BIT-DQ6 The MX28F2000P features a "Toggle Bit" method to indicate to the host sytem that the Auto Program/ Erase algorithms are either in progress or completed. While the Automatic Program or Erase algorithm is in ...
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... The Data Polling feature is active during Automatic Program/Erase algorithms. POWER-UP SEQUENCE The MX28F2000P powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Power up sequence is not required. ...
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... Specifications contained within the following tables are sub- -0.5V to 7.0V ject to change. -0.5V to 7.0V -0.5V to 13.5V MIN. TYP VCC = 5V ± 10%, VPP = GND to VCC MIN. TYP 1 1 -0.3 (NOTE 1) 2.4 2.4 11 MX28F2000P MAX. UNIT CONDITIONS 14 pF VIN = VOUT = 0V MAX. UNIT CONDITIONS 10 uA VIN = GND to VCC 10 uA VOUT = GND to VCC 100 uA VPP = 5 ...
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... Note1 NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. ACTIVE MODE tCE tOE tACC 12 MX28F2000P MAX. UNIT CONDITIONS 120 ns CE=OE=VIL 120 ns OE=VIL 50 ns CE=VIL CE=VIL 0 ns ...
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... TYP 1 -0.3 (Note 5) 2.4 2.4 5. VIL min. = -0.6V for pulse width < 20ns VIH is over the specified maximum value, programming operation cannot be guranteed. 7. All currents are in RMS unless otherwise noted.(Sampled, not 100% tested.) 13 MX28F2000P MAX. UNIT CONDITIONS 10 uA VIN=GND to VCC 10 uA VOUT=GND to VCC 1 ...
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... MX28F2000P 28F2000P-12 MAX. MIN. MAX. UNIT CONTIONS 100 ns 100 ns 120 100 100 100 ...
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... CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORMS 2 TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". P/N: PM0380 CL 6.2K ohm 2.0V TEST POINTS 0.8V INPUT Input pulse rise and fall times are <20ns. 15 MX28F2000P 1.8K ohm +5V DIODES = IN3064 OR EQUIVALENT 2.0V 0.8V OUTPUT REV. 1.5, OCT 29, 1998 ...
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... Auto program & DATA polling program command Address valid tAS tAVT tCWC tCEPH1 tCEP tCEP tCESP tCES tDS tDH tDS tDH tDPA Command in Data in DATA polling Command in Data in Command #40H 16 MX28F2000P tVPH tAH1 tCESC tDF DATA DATA DATA REV. 1.5, OCT 29, 1998 ...
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... AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART P/N: PM0380 START Apply VppH Write Set up auto program Command (40H) Write Auto program Command(A/D) NO Toggle Bit Checking DQ6 not Toggled YES NO Verify Byte Ok YES NO Last Byte YES Auto Program Completed 17 MX28F2000P Reset Auto Program Failed REV. 1.5, OCT 29, 1998 ...
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... Setup auto chip erase/ Auto chip erase & DATA polling erase command tAETC tCWC tCESP tCES tCEP tCEP tCEPH1 tDS tDH tDS tDH tDPA Command in Command in DATA polling Command in Command in Command #30H Command #30H 18 MX28F2000P tVPH tCESC tDF REV. 1.5, OCT 29, 1998 ...
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... AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART Write Set up auto chip Erase Command (30H) P/N: PM0380 START Apply VppH Write Auto chip Erase Command(30H) Toggle Bit Checking No DQ6 not Toggled YES DATA Polling No DQ7 = 1 YES Auto Chip Erase Completed 19 MX28F2000P Reset Auto Chip Erase Failed REV. 1.5, OCT 29, 1998 ...
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... Setup auto block erase/erase command Block Block address 0 address 1 tAS tAH tBALC tBAL tCEPH1 tCEP tCEPH2 tDH tDS tDH Command in Command in 20 MX28F2000P Auto block erase & DATA polling tVPH Block address # tAH1 tCESC tAETB tDF tDPA DATA polling REV. 1.5, OCT 29, 1998 ...
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... Write Auto block Erase Command(D0H) to Load Block Address Load Block Address Last Block NO to Erase YES Wait 200 us Toggle Bit Checking NO DQ6 not Toggled YES NO DATA Polling DQ7 = 1 YES Auto Block Erase Completed 21 MX28F2000P Reset Auto Block Erase Failed REV. 1.5, OCT 29, 1998 ...
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... Command #20H Command #20H P/N: PM0380 Setup chip erase/ Chip erase erase command tET tCWC tCEP tCEPH1 tDH tDS tDH Command in Command in Command in Command in 22 MX28F2000P Erase Verify tVPH Verify Address tAS tAH tCESV tCESC tCEP tCES tVA tDH tDS tDF Command in Data valid ...
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... VPP = VCC END BLOCK ERASE COMPLETE START Apply VPP = VPPH WRITE SETUP BLOCK ERASE COMMAND ( 60H ) WRITE BLOCK ERASE COMMAND ( LOAD FIRST SECTOR ADDRESS , 60H ) LOAD OTHER SECTORS' ADDRESS IF NECESSARY ( LOAD OTHER SECTOR ADDRESS ) WAIT 10 ms END 23 MX28F2000P N = N+1 NO REV. 1.5, OCT 29, 1998 ...
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... ERASE VERIFY FLOW INCREMENT ADDRESS P/N: PM0380 MX28F2000P START APPLY VPP = VPPH ADDRESS = FIRST ADDRESS OF ERASED BLOCKS OR LAST VERIFY FAILED ADDRESS WRITE ERASE VERIFY COMMAND ( A0H ) WAIT ERSVFY FFH ? YES NO LAST ADDRESS ? YES ERASE VERIFY COMPLETE ERASE FLOW AGAIN OR ABORT ...
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... Command in Q0~Q6 Command in Command #60H Command #60H P/N: PM0380 Block Block address 1 address # tBALC tBAL tCEP tCEPH2 tDS tDH Command in Command in 25 MX28F2000P Block erase Erase Verify tVPH Verify address Verify address tAS tAH tET tCESV tCESC tCEP tCES tDS tVA tDH tDF ...
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... VIL A10-A17 tACC VIH WE CE tCE P/N: PM0380 Address valid tCWC tACC tCEPH1 tCE tDH tOE 00H tACC tOE tOH Manufacturer code C2H 26 MX28F2000P tVPH tCESC tOES tDF tOH Data out valid tDF tOH Device code 2AH REV. 1.5, OCT 29, 1998 ...
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... OE Q0-Q7 P/N: PM0380 Address Valid tCWC tACC tCEP tCEPH2 tCE tDS tDH tOE Command in 90H tCWC tCEP tCEP tCEPH1 tDS tDH tDS tDH Command in Command in FFH FFH 27 MX28F2000P tVPH tCESC tOES tDF tOH Data out valid C2H or 2AH REV. 1.5, OCT 29, 1998 ...
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... Toggle bit appears in Q6, when program/erase is opperating. DATA polling appears in Q7 during pro- gramming or erase. HIGH WE Vpp 12V HIGH-Z DURING P/E HIGH-Z Q7 DATA DURING P HIGH-Z Q7 DURING E HIGH-Z Q0~Q5 P/N: PM0380 TOGGLE BIT DATA POLLING DATA PROGRAM/ERASE COMPLETE 28 MX28F2000P DATA DATA DATA DATA POLLING DATA REV. 1.5, OCT 29, 1998 ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX28F2000PPC-70C4 70 MX28F2000PPC-90C4 90 MX28F2000PPC-12C4 120 MX28F2000PQC-70C4 70 MX28F2000PQC-90C4 90 MX28F2000PQC-12C4 120 MX28F2000PTC-70C4 70 MX28F2000PTC-90C4 90 MX28F2000PTC-12C4 120 MX28F2000PRC-70C4 70 MX28F2000PRC-90C4 90 MX28F2000PRC-12C4 120 P/N: PM0380 MX28F2000P OPERATING STANDBY PACKAGE CURRENT CURRENT MAX.(mA) MAX.(uA) 50 100 32 Pin DIP 50 100 32 Pin DIP 50 100 32 Pin DIP ...
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... K .46 [REF] .018 [REF] L 10.40/12.94 .410/.510 (W) (L) (W) (L) M .89R .035R N .25[Typ.] .010[Typ.] NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP maximum at maximum material condition. P/N: PM0380 MX28F2000P ...
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... K 1.00 ± .10 .039 ± .004 L 1.27 max. .050 max. M .50 .020 N 0 ~5° .500 NOTE: Each lead certerline is located within .25mm[.01 inch] of its true position [TP maximum at maximum material condition. P/N: PM0380 MX28F2000P REV. 1.5, OCT 29, 1998 L ...
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... Command description of dummy mode a added, TSOP pin configuration diagram rotated 180°, the flow chart of block erase corrected, fast acces time 150ns removed. 1.4 The speed performanes is featured up to 70ns as the new update of fast access time 1.5 To corret typing error P/N: PM0380 MX28F2000P 32 Page Date P1,14,29 Sep/18/98 P12,14,16, OCT/29/98 27,29 REV. 1.5, OCT 29, 1998 ...
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... TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 33 MX28F2000P ...