MX29F001T Macronix, MX29F001T Datasheet - Page 7

• Manufacturer Part Number: MX29F001T
• Description: 1M bit CMOS Flash Memory
• Manufacturer: Macronix

READ/RESET COMMAND
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The de-
vice remains enabled for reads until the command regis-
ter contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.
The MX29F001T/B contains a Silicon-ID-Read operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the read sili-
con ID command sequence into the command register.
Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 18H for MX29F001T,19H for MX29F001B.
TABLE 3. EXPANDED SILICON ID CODE
P/N: PM0515
Code
Manufacture code
Device code
for MX29F001T
Device code
for MX29F001B
Chip Protection Verification
Pins
VIH
VIH
VIL
A0
X
X
VIH
VIH
VIL
VIL
VIL
A1
Q7
0
0
0
0
1
Q6
0
1
0
0
0
7
SET-UP AUTOMATIC CHIP ERASE COM-
MANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verification begin. The
erase and verification operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system does not require to pro-
vide any control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verify command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating an erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
Q5
0
0
0
0
0
Q4
0
0
1
1
0
Q3
0
0
1
1
0
MX29F001T/B
Q2
0
0
0
0
0
Q1
0
1
0
0
0
Q0
1
0
0
1
0
00H (Unprotected)
01H (Protected)
REV. 2.5,NOV. 20, 2002
Code (Hex)
C2H
18H
19H