74LCX74M Fairchild Semiconductor, 74LCX74M Datasheet

IC FLIP FLOP LV DUAL D 14-SOIC

74LCX74M

Manufacturer Part Number
74LCX74M
Description
IC FLIP FLOP LV DUAL D 14-SOIC
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Type
D-Typer
Datasheets

Specifications of 74LCX74M

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
150MHz
Delay Time - Propagation
7ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Circuits
2
Logic Family
74LC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
8 ns
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Flip-flop Type
D
Propagation Delay
7ns
Frequency
150MHz
Output Current
24mA
Ic Output Type
Complementary
Supply Voltage Range
2V To 3.6V
Logic Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©1995 Fairchild Semiconductor Corporation
74LCX74 Rev. 1.7.0
74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop with 5V Tolerant Inputs
Features
Ordering Information
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LCX74M
74LCX74SJ
74LCX74BQX
74LCX74MTC
5V tolerant inputs
2.3V–3.6V V
7.0ns t
Power down high impedance inputs and outputs
±24mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
– Machine model
Leadless Pb-Free DQFN package
Order Number
All packages are lead free per JEDEC: J-STD-020B standard.
PD
max. (V
(1)
CC
specifications provided
CC
200V
CC
3.3V), 10µA I
Package
Number
2000V
MLP14A
MTC14
M14D
M14A
3.0V)
CC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
max.
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
and Q HIGH
Package Description
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
D
and S
D
makes both Q
www.fairchildsemi.com
March 2008

Related parts for 74LCX74M

74LCX74M Summary of contents

Page 1

... M14A 74LCX74SJ M14D (1) 74LCX74BQX MLP14A 74LCX74MTC MTC14 Note: 1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev ...

Page 2

... Pin Assignments for SOIC, SOP, and TSSOP Pad Assignment for DQFN (Top View) Pin Description Pin Names Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 Logic Symbols IEEE/IEC Truth Table (Each Half) Inputs ...

Page 3

... CC V 2.7V–3. 2.3V–2. Free-Air Operating Temperature Input Edge Rate, V Note: 3. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 Parameter (2) GND I (3) Parameter 0.8V–2.0V Rating –0.5V to +7.0V –0.5V to +7.0V – ...

Page 4

... Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 V (V) Conditions CC 2.3– ...

Page 5

... Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 V (V) Conditions CC 3.3 C 50pF, V 3.3V 2.5 C 30pF, V 2.5V 3.3 C 50pF ...

Page 6

... Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t 3-STATE Output High Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics 1MHz, t ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 (Generic for LCX Family) includes probe and jig capacitance) L ...

Page 7

... Schematic Diagram (Generic for LCX Family) ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 7 www.fairchildsemi.com ...

Page 8

... BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) ©1995 Fairchild Semiconductor Corporation 74LCX74 Rev. 1.7.0 Tape Section Number of Cavities 125 (Typ.) Carrier 3000 75 (Typ 0.512 (13.00) 0.795 (20.20) ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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