spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 40

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
2-14
Notes:
No.
115
116
117
118
119
Address valid to RD
assertion
RD assertion pulse width
RD deassertion to address
not valid
TA setup before RD or WR
deassertion
TA hold after RD or WR
deassertion
1.
2.
3.
4.
5.
6.
Characteristics
WS is the number of wait states specified in the BCR.
Timings 100, 107 are guaranteed by design, not tested.
All timings for 100 MHz are measured from 0.5 · Vcc to 0.5 · Vcc
Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active.
Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz.
V
CC
4
= 3.3 V ± 0.3 V; T
Note: Address lines A[0–23] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
A[0–23]
D[0–23]
AA[0–3]
WR
RD
TA
Table 2-8.
J
Symbol
= –40°C to +100°C, C
Figure 2-12.
SRAM Read and Write Accesses
DSP56301 Technical Data, Rev. 10
113
0.25 × T
1.25 × T
2.25 × T
(WS + 0.25) × T
L
= 50 pF
0.25 × T
Expression
0.5 × T
C
C
− 2.0 [1 ≤ WS ≤ 3]
− 2.0 [4 ≤ WS ≤ 7]
C
SRAM Read Access
− 2.0 [WS ≥ 8]
104
C
C
− 4.0
+ 2.0
C
1
−4.0
100
105
116
3,6
Min
11.6
13.6
26.1
(Continued)
118
2.3
1.1
5.1
0
80 MHz
Data
In
Max
—
—
—
—
—
—
—
Freescale Semiconductor
117
106
119
Min
10.5
20.5
1.0
8.5
0.5
4.5
0
100 MHz
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns