spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 9

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

1.3 Clock
1.4 Phase Lock Loop (PLL)
Freescale Semiconductor
Ground Name
GND
GND
GND
Note:
EXTAL
XTAL
CLKOUT
PCAP
Signal Name
Signal Name
N
H
S
These designations are package-dependent. Some packages connect all GND inputs except GND
internally. On those packages, all ground connections except GND
Bus Control Ground
Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Host Ground
Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections.
The user must provide adequate external decoupling capacitors.
ESSI, SCI, and Timer Ground
Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Input
Output
Output
Input
Type
Type
Chip-driven
Input
Chip-driven
Input
State During
State During
Table 1-5.
Reset
Reset
DSP56301 Technical Data, Rev. 10
Table 1-4.
Table 1-3.
External Clock/Crystal Input
Interfaces the internal crystal oscillator input to an external crystal or an
external clock.
Crystal Output
Connects the internal crystal oscillator output to an external crystal. If an
external clock is used, leave XTAL unconnected.
Clock Output
Provides an output clock synchronized to the internal core clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PLL Capacitor
Connects an off-chip capacitor to the PLL filter. Connect one capacitor
terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP can be tied to V
Phase Lock Loop Signals
Clock Signals
Grounds
Description
P
and GND
P1
Signal Description
Signal Description
are labeled GND.
CCP
CC
P
, GND, or left floating.
.
and GND
P1
to each other
Clock
1-5