spakdsp301vl100 Freescale Semiconductor, Inc, spakdsp301vl100 Datasheet - Page 71

• Manufacturer Part Number: spakdsp301vl100
• Description: Dsp56301 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Notes:
No.
1.
2.
3.
4.
5.
6.
7.
8.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and
the ESSI control register.
The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync signal
waveform, but spreads from one serial clock before the first bit clock (same as Bit Length Frame Sync signal), until the one
before the last bit clock of the first word in frame.
Periodically sampled and not 100 percent tested
V
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode
i ck s = Internal Clock, Synchronous Mode
bl = bit length
wl = word length
wr = word length relative
If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5 ×
T
C
CC
).
Characteristics
= 3.3 V ± 0.3 V; T
(Asynchronous implies that TXC and RXC are two different clocks)
(Synchronous implies that TXC and RXC are the same clock)
J
4, 5, 7
= −40°C to +100 °C, C
Table 2-22.
DSP56301 Technical Data, Rev. 10
Symbol
L
ESSI Timings (Continued)
= 50 pF
Expression
Min
80 MHz
Max
AC Electrical Characteristics
Min
100 MHz
Max
Cond-
ition
6
Unit
2-45