stv7622 STMicroelectronics, stv7622 Datasheet
stv7622
Related parts for stv7622
stv7622 Summary of contents
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... BCD Process Packaging according to customer request: wafer, die, bumped die/wafer, TCP or COF Description The STV7622 is a data driver for Plasma Display Panels (PDP) designed in the ST’s proprietary BCD high-voltage technology. It controls up to 192 outputs via an input data bus ( 3-bits wide) operating 60MHz. ...
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... Differential transmission mode: RSDS (BS1 = L, BS2 = 5.6 Power output block and EMI control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Pad dimensions and positions (in µ Tested wafer disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 STV7622 ...
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... STV7622 1 Block diagram Figure 2. STV7622 block diagram BS1 BS2 DB1 DB2 DB3 DB4 DB5 DB6 Data decoding /STB1 /STB2 /BLK POC OUT1 OUT2 DIR CLK1 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register 32-bit Shift register ...
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... Shift register configuration pins (3/6/2 Clock for data shift register Latch of data to power outputs Output rise time selection pins Output “slow-slope” fall time selection pins Must be grounded Must be grounded Filter for internal reference - must be connected to ground via a 10nF capacitor STV7622 3-bits and RSDS selection) ...
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... STV7622 3 Output stage description Figure 3. Output stage description VCC Rise time RS1/RS2 VCC Fall time FS1/FS2 Output stage T3 Rising edge control Delay Falling edge T4 control Output control Output stage description VPP Totem pole T1 OUTn T2 VSSP 5/32 ...
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... TEST1 and TEST2 are used to test the device. For good test coverage, they must not be shorted together on the TCP. In the application, TEST1 and TEST2 must be grounded at the TCP connector level. VREF must be connected to ground via a 10nF filter capacitor. 6/32 Y 0/0 X Figure 4 above: STV7622 VSSP4 VSSP5 VSSP6 VPP4 VPP5 VPP6 DUMMY VSSLOG2 VSSSUB2 ...
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... All output data is stored and held in the latch stage when the latch input is pulled back High. The core of the STV7622 is powered by 5V. All logic inputs can be driven either 3.3V CMOS logic. The tables in the following sections describe the position of the first data sampled by the first rising edge of the CLK1 clock ...
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... Right/Left … Comment 175 181 187 176 182 188 177 183 189 178 184 190 179 185 191 180 186 192 STV7622 shift shift Left/Right shift Right/Left shift ...
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... STV7622 5 32-bit data bus, standard transmission (BS1 = H, BS2 = H) The data bus below describes how data is shifted in the register. Table 32-bit data bus transmission BS1 BS2 DIR Input Position DB1 DB2 DB3 DB4 DB5 DB6 DB1 ...
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... When operating in differential transmission mode, a 100 ohm (1%) resistor termination must be connected between: DB1 and DB2 DB3 and DB4 DB5 and DB6 CLK1 and CLK2 STB1 and STB2 with each resistor placed as close as possible to the STV7622 itself. 10/32 CLK1 clock pulse number … ...
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... Differential input buffer - waveform timing OUTn STV7622 TCP STLVD31 Video board DB1-3-5 Differential V input buffer ID DB2-4-6 (=DB1-3- PHLD 90% 50% 10 STV7622 TCP Data driver board STLVD31 Display controller Circuit description V 0 1.4V 1.0V 0.4V -0.4V t PLHD 90% 50% 10 STV7622 TCP STLVD31 11/32 ...
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... N-channel transistor, T2. The status of the power outputs can also be controlled by the configuration pins, POC and /BLK, which can set the power outputs either all High or all Low. Several functions, patented by STMicroelectronics, are implemented in the STV7622 to reduce EMI: SmartSlope: The falling edge of the output pulse consist of 2 slopes ...
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... Spread Spectrum: To avoid having too large of a current in the driver during the rising edge of the power outputs, all outputs are not triggered at the same time. Instead, the STV7622 inserts a small delay between the rising edge of two consecutive outputs. This delay depends on picture or image content (see ...
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... DB1,2, 6 input pins, RSDS mode Steady Left /Right shift, DB1,2, N. N.C. Steady Left /Right shift, DB1,2, 6 input pins, N. N.C. Steady STV7622 Shift register function Q output 32-bit mode 32-bit mode 64-bit mode 64-bit mode 6 input pins, 3 32-bit mode 3 32-bit mode ...
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... STV7622 Table 8. Truth table for power outputs (1) (2) Q /STB1 /STB2 the state of the shift register output n 2. /STB2 is not used in LVCMOS operating mode and can be left “open” or “floating”. ...
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... These parameters are measured during STMicroelectronics’ internal qualification which includes temperature characterization on standard as well as corner batches of the process. These parameters are not tested in production. 4. VCC pins withstand 1.3 KV. 16/32 Parameter (1), (2), (3) (1), (2), (3) STV7622 Value Units -0. -0. -0.3, + ...
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... STV7622 8 Electrical characteristics VCC = VDD = 5V, VPP = 70V, VSSP = VSSLOG = VSSSUB = 0V MHz, unless otherwise specified. CLK Table 10. Electrical characteristics Symbol Supply Vdd Digital supply voltage Idd Digital supply current Iddl Digital Dynamic Supply Current (CLK1 freq = 20MHz) Idd Digital Supply Current @ V ...
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... Same for TTL and RSDS modes. This parameter is measured during qualification by ST Microelectronics which includes temperature characterization on standard as well as corner batches of the process. This parameter is not tested in production. Figure 9. Output test configuration OFF (*) Output sinking current is considered as positive. 18/32 Parameter VPP ON Vdouth Idouth (*) OUTn + VSSP/VSSSUB STV7622 Min. Typ. Max. 100 400 600 0.5 V 1 VPP OFF ...
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... STV7622 9 AC timing requirements VCC = VDD = 4.5V to 5.5V, Tamb = -20° +85°C, input signal edge maximum rise and fall times (tr, tf) = 3ns. Table 11. AC timing requirements Symbol t Data clock period CLK t Duration of clock pulse at high level WHCLK t Duration of clock pulse at low level WLCLK ...
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... FS2 = “H”) VCC. Min Typ Max - 35 100 - 30 100 - 120 150 180 230 280 320 400 480 470 560 670 50 - 200 100 120 160 200 240 STV7622 Units ...
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... STV7622 Figure 10. AC characteristic waveforms Standard mode CLK DB (input) t STB 50% /STB ) OUT(n / BLK OUTn (See sections on output falling/rising edge) Differential mode CLK1 CLK2 DB1-3-5 (input) DB2-4-6 (input) t STB /STB1 50% /STB2 t CLK t t WHCLK 50% 50% t HSTB 50% 50% t SSTB t PHL2 90% 10% t PLH2 50% ...
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... STV7622 Bump dimensions X Y 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43 ...
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... STV7622 Table 13. Pad placement and bump pad dimensions (in microns) (continued) Lead pad name OUT165 OUT164 OUT163 OUT162 OUT161 OUT160 OUT159 OUT158 OUT157 OUT156 OUT155 OUT154 OUT153 OUT152 OUT151 OUT150 OUT149 OUT148 OUT147 OUT146 OUT145 OUT144 OUT143 OUT142 OUT141 OUT140 OUT139 OUT138 ...
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... STV7622 Bump dimensions X Y 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43 ...
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... STV7622 Table 13. Pad placement and bump pad dimensions (in microns) (continued) Lead pad name OUT99 OUT98 OUT97 OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 ...
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... STV7622 Bump dimensions X Y 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43 ...
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... STV7622 Table 13. Pad placement and bump pad dimensions (in microns) (continued) Lead pad name OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 ...
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... STV7622 Bump dimensions X Y 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43 ...
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... STV7622 Table 13. Pad placement and bump pad dimensions (in microns) (continued) Lead pad name FS2 VSSLOG5 RS2 VDD5 RS1 VSSLOG4 DUMMY VREF DUMMY DUMMY VDD4 POC VSSLOG3 BLK/ VDD3 CLK1 CLK2 STB1/ STB2/ DB1 DB2 DB3 DB4 DB5 DB6 Pad dimensions and positions (in µm) ...
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... LEFT SIDE from bottom to top VCC1 VDD1 VSSSUB1 VSSLOG1 DUMMY VPP3 VPP2 VPP1 VSSP3 VSSP2 VSSP1 30/32 Pad placements X Y -7474.9 -555.2 -7474.9 -189.2 -7474.9 -114.3 -7474.9 -39.4 -7474.9 35.5 -7474.9 110.3 -7474.9 185.2 -7474.9 260.1 -7474.9 485.5 -7474.9 560.3 -7462.9 635.2 STV7622 Bump dimensions X Y 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 65.6 43.5 ...
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... Please remember that it is the customer’s responsibility to test and qualify their application using the STMicroelectronics die. STMicroelectronics is ready to support customers when qualifying the product. 13 Ordering information Table 14. Order codes Part number STV7622/BMP 14 Revision history Table 15. Document revision history Date 29-May-2007 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 32/32 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STV7622 ...