cy2vc511 Cypress Semiconductor Corporation., cy2vc511 Datasheet

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cy2vc511

Manufacturer Part Number
cy2vc511
Description
Cy2vc511 Low Noise Clock Generator With Vcxo
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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cy2vc511ZXC
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cy2vc511ZXC
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Features
Cypress Semiconductor Corporation
Document Number: 001-10796 Rev. *D
Logic Block Diagram
Generates 27 MHz Output Clock
Uses 27 MHz LVCMOS Reference Clock
LVCMOS Output
VCXO with 230 ppm Minimum Pull Range
Fully Integrated Low Noise Phase Locked Loop (PLL)
Linear Voltage-to-Frequency Control Curve
Supply Voltage: 3.3V
Pb-free 16-Pin TSSOP Package
REFIN
VIN
PRELIMINARY
198 Champion Court
27 MHz Clock Generator with VCXO
LOW -NOISE
PLL
Description
The CY2VC511 is a PLL based clock generator with VCXO
control. It takes a low swing 27 MHz reference clock, and
generates an adjustable 27 MHz output clock. The device has a
single LVCMOS output and operates from a 3.3V power supply.
The VIN pin is an analog input that enables the user to pull the
output frequency. The pullability range is at least 230 ppm (±115
ppm). The pull curve is very linear.
Unlike conventional VCXO designs, the output frequency
adjustment is achieved by a proprietary PLL design. This permits
the use of 27 MHz clock reference.
San Jose
,
CA 95134-1709
CLK
Revised May 14, 2010
CY2VC511
408-943-2600
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cy2vc511 Summary of contents

Page 1

... Document Number: 001-10796 Rev. *D PRELIMINARY 27 MHz Clock Generator with VCXO Description The CY2VC511 is a PLL based clock generator with VCXO control. It takes a low swing 27 MHz reference clock, and generates an adjustable 27 MHz output clock. The device has a single LVCMOS output and operates from a 3.3V power supply. ...

Page 2

... VIN causes the output frequency to increase The nominal output frequency is determined when VIN = 1.65V 27 MHz Output Clock Do Not Use: DNU pins are electrically connected, but perform no function No Connect: NC pins are not connected to the die Supply Voltage: 3.3V Ground CY2VC511 Page [+] Feedback ...

Page 3

... Ensure the layout is optimized to minimize power and ground inductance and locate the capacitor as close to the device pins as possible. Condition Relative Non operating JEDEC STD 22-A114 m/s airflow 1 m/s airflow 2.5 m/s airflow Description CY2VC511 Output Frequency (MHz) 27 Min Max Unit –0.5 4.4 V –0 0 ° ...

Page 4

... Time for CLK to reach valid frequency measured from the time (min Figure 2. Output Duty Cycle Timing PERIOD Figure 3. Output Rise and Fall Time 80% 80% 20% 20 CY2VC511 Min Typ Max Unit – – 110 0.9*V – – DD – – 0.1*V DD 1.25 – 1.8 – ...

Page 5

... Part Number Pb-Free CY2VC511ZXC 16-Pin TSSOP CY2VC511ZXCT 16-Pin TSSOP - Tape and Reel Package Drawings and Dimensions Document Number: 001-10796 Rev. *D PRELIMINARY Package Description Figure 4. 16-Pin TSSOP 4.40 mm Body CY2VC511 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C 51-85091 *B Page [+] Feedback ...

Page 6

... Document History Page Document Title: CY2VC511 27 MHz Clock Generator with VCXO Document Number: 001-10796 Orig. of Submission Rev. ECN No. Change Date ** 506248 RGL See ECN *A 1285703 JWK/KVM/ See ECN ARI *B 2705638 XHT/KVM/ 05/13/2009 AESA *C 2768029 KVM 09/18/2009 *D 2905106 KVM 05/14/10 Document Number: 001-10796 Rev. *D ...

Page 7

... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-10796 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. PRELIMINARY cypress.com/go/plc Revised May 14, 2010 CY2VC511 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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