cy2v995 Cypress Semiconductor Corporation., cy2v995 Datasheet
cy2v995
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cy2v995 Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-07435 Rev. *A 2.5/3.3V 200-MHz Multi-Output Description The CY2V995 is a low-voltage, low-power, eight output, 200-MHz clock driver. It features function necessary to optimize the timing of high-performance computer and communication systems. The user can program the frequency of the output banks through nF[0:1] and DS[0:1] pins. Any one of the outputs can ...
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... Power DD 9-12, 22-25 PWR Power SS Device Configuration The outputs of the CY2V995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 1. Notes: 1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. ...
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... Table 7. PE Settings The CY2V995 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core 2 power supply (V than that on any one of the output power supplies. [6] 1 Table 8 ...
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... Max, (sOE 12mA, (nQ[0:1 2mA (LOCK –12mA,(nQ[0:1 –2mA (LOCK) OH VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH V = Max DD @100 MHz CY2V995 Min. Max. Unit 2.25 2.75 V 2.97 3. – 0.3 – – 0 5.5 V 4.6 V – ...
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... LOW, sOE# = LOW, Outputs not loaded PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH V = Max DD @100 MHz Condition 0.8V – 2.0V HIGH or LOW FS = LOW FS = MID FS = HIGH Condition Skew between the earliest and the latest output transitions within the same bank. CY2V995 Min. Max. Unit 2.97 3.63 V – 0.8 V 2.0 – –-0.6 – V ...
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... Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V–1.7V for VDD = 2.5V Divide by 1 output frequency divide by any Divide by 1 output frequency M/ divide by any CY2V995 Min. Max. Unit – 200 ps – 200 ps – ...
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... AC Timing Definitions t PWH REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document #: 38-07435 Rev REF t PWL t t 0DCV 0DCV t t SKEWPR SKEWPR t SKEW0,1 t SKEW0 SKEW1 SKEW1 t SKEW3 t SKEW3 t SKEW1,3,4 CY2V995 t CCJ1-12 t SKEW3 t SKEW1,3,4 Page [+] Feedback ...
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... For All Other Outputs Figure 1. t OFALL 1.7V VTH =1.25V 0.7V Figure 2. ≤ 1ns 2.5V 1.7V VTH =1.25V 0.7V 2.5V LVTTL INPUT TEST WAVEFORM Figure 3. Package Type CY2V995 150Ω 20pF 150Ω ORISE OFALL t PWH t PWL 2.5V LVTTL OUTPUT WAVEFORM ≤ 1ns ≤ 1ns 0V Product Flow Commercial, 0° ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2V995 51-85155-*A ...
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... Document History Page Document Title:CY2V995 2.5/3.3V 200-MHz Multi-output Zero Delay Buffer Document Number: 38-07435 REV. ECN No. Issue Date ** 122627 01/13/03 *A 200501 See ECN Document #: 38-07435 Rev. *A Orig. of Description of Change Change RGL New Data Sheet Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin ...