cy2v995 Cypress Semiconductor Corporation., cy2v995 Datasheet - Page 2

• Manufacturer Part Number: cy2v995
• Description: 2.5/3.3v 200-mhz Multi-output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07435 Rev. *A
Pin Description
Device Configuration
The outputs of the CY2V995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback
input divider is controlled by the 3-level DS[0:1] pins as
indicated in Table 1.
Notes:
39
17
37
2
4
34, 33, 36, 35,
43, 42, 1, 44
41
26,27,20,21,
13,14,7,8
32, 31
3
30
5,6
15,16
19,28
18,40
9-12, 22-25, 38 V
1.
2.
3.
4.
‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
Permissible output division ratios connected to FB. The frequency of the REF input will be F
using an undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
Pin
REF
FB
TEST
sOE#
PE
nF[1:0]
FS
nQ[1:0]
DS[1:0]
PD#
LOCK
V
V
V
V
DD
DD
DD
SS
Name
DD
Q3
Q1
[2]
Q4
[2]
[2]
[2]
I
I
I
I, PD
I, PU
I
I
O
I
I, PU
O
PWR
PWR
PWR
PWR
PWR
I/O
[1]
LVTTL/
LVCMOS
LVTTL
3-Level
LVTTL
LVTTL
3-Level
3-Level
LVTTL
3-Level
LVTTL
LVTTL
Power
Power
Power
Power
Power
Type
Reference Clock Input.
Feedback Input.
When MID or HIGH, disables PLL (except for conditions of note 3). REF
goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used
as the feedback signal to maintain phase lock. When TEST is held at MID
level and sOE# is high, the nF[1:0] pins act as output disable controls for
individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. Please see
Table 8.
Select frequency of the outputs. Please see Tables 3, 4, 5, and 7.
Selects VCO operating frequency range. Please see Table 6.
Four banks of two outputs. Please see Table 5 for frequency settings.
Select feedback divider. Please see Table 1.
Power-down and reference divider control. When LOW, shuts off entire
chip. Please see Table 2 for settings.
PLL lock indication signal. HIGH indicates lock. LOW indicates that the
PLL is not locked and outputs may not be synchronized to the input.
Power supply for Bank 4 output buffers. Please see Table 8 for supply
level constraints
Power supply for Bank 3 output buffers. Please see Table 8 for supply
level constraints
Power supply for Bank 1 and Bank 2 output buffers. Please see Table 8
for supply level constraints
Power supply for the internal circuitry. Please see Table 8 for supply level
constraints
Ground
Table 1. Feedback Divider Settings
DS[1:0]
MM
MH
HM
LM
ML
HH
LH
HL
LL
NOM
N-Feedback Input
/N when the part is configured for frequency multiplication by
Description
Divider
10
12
2
3
4
5
1
6
8
Permitted Output Divider
Connected to FB
1,2 or 4
1,2 or 4
1 or 2
1 or 2
1 or 2
1 or 2
CY2V995
1
1
1
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