cy2cp1504 Cypress Semiconductor Corporation., cy2cp1504 Datasheet

Page 1

... CY2CP1504 low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2CP1504 can select between two separate LVCMOS input clocks using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a ...

Page 2

... Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Dimension........................................................ 10 Acronyms ........................................................................ 11 Document Number: 001-56313 Rev. *F Document Conventions ................................................. 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 CY2CP1504 Page [+] Feedback ...

Page 3

... When IN_SEL = Low, input IN0 is active When IN_SEL = High, input IN1 is active LVCMOS input clock. Active when IN_SEL = Low No connection LVCMOS input clock. Active when IN_SEL = High Power supply LVPECL complementary output clocks LVPECL output clocks CY2CP1504 Description Page [+] Feedback ...

Page 4

... Document Number: 001-56313 Rev. *F Condition Nonfunctional Nonfunctional SS Nonfunctional SS Nonfunctional JEDEC STD 22-A114-B At 1/8 in Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for V DD minimum specified voltage (power ramp must be monotonic) CY2CP1504 Min Max Unit –0.5 4.6 V –0.5 lesser of 4 0.4 DD –0.5 lesser of 4 0.4 DD – ...

Page 5

... 2 [3] Input = V DD [3] Input = V SS Terminated with 50 Ω [4] – 2.0 DD Terminated with 50 Ω [4] – 2.0 DD CLK_EN has pull-up only IN_SEL has pull-down only Measured at 10 MHz; per pin CY2CP1504 Min Max Unit – 2 0 –0.3 0 –0.3 0.7 V μ ...

Page 6

... DD 50% duty cycle at input, 20% to 80% of full swing ( Input rise/fall time < 1.5 ns (20% to 80%) Synchronous clock enable (CLK_EN) switched Low Synchronous clock enable (CLK_EN) switched high CY2CP1504 Min Typ Max Unit DC – 250 MHz DC – 250 MHz 600 – ...

Page 7

... Figure 5. Output-to-Output and Device-to-Device Skew Device Device Document Number: 001-56313 Rev. *F Figure 2. Output Differential Voltage Figure 4. Output Duty Cycle PERIOD ODC t PERIOD t SK1 t SK1 D CY2CP1504 Page [+] Feedback ...

Page 8

... Document Number: 001-56313 Rev. *F Figure 6. RMS Phase Jitter Phase noise Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 7. Output Rise/Fall Time 80% 80% 20 Figure 8. Synchronous Clock Enable Timing CY2CP1504 Phase noise mark SOE Page [+] Feedback ...

Page 9

... Pb-free TSSOP package Number of differential output pairs Base part number Company ID Cypress Document Number: 001-56313 Rev. *F Type Commercial, 0 ° °C Commercial, 0 ° °C Industrial, –40 ° °C Industrial, –40 ° °C CY2CP1504 Production Flow Page [+] Feedback ...

Page 10

... Package Dimension Figure 9. 20-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ20 Document Number: 001-56313 Rev. *F CY2CP1504 51-85118 *C Page [+] Feedback ...

Page 11

... Unit of Measure °C degree Celsius dBc decibels relative to the carrier GHz giga hertz Hz hertz kΩ kilo ohm µA microamperes µF micro Farad µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts CY2CP1504 Page [+] Feedback ...

Page 12

... Document History Page Document Title: CY2CP1504 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-56313 Orig. of Submission Revision ECN Change ** 2782891 CXQ *A 2838916 CXQ *B 3011766 CXQ *C 3017258 CXQ *D 3100234 CXQ *E 3137726 CXQ *F 3182321 CXQ Document Number: 001-56313 Rev. *F Description of Change ...

Page 13

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56313 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 25, 2011 CY2CP1504 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...