cy2cp1504 Cypress Semiconductor Corporation., cy2cp1504 Datasheet - Page 12

• Manufacturer Part Number: cy2cp1504
• Description: 1 4 Lvcmos To Lvpecl Fanout Buffer With Selectable Clock Input
• Manufacturer: Cypress Semiconductor Corporation.

Document History Page
Document Number: 001-56313 Rev. *F
Revision
Document Title: CY2CP1504 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56313
*C
*D
*A
*B
*E
*F
**
2782891
2838916
3011766
3017258
3100234
3137726
3182321
ECN
Change
Orig. of
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
CXQ
Submission
05/01/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
08/20/2010 Changed from 0.25 ps to 0.15 ps maximum additive jitter in “Features” on page
08/27/2010 Corrected Output Rise/Fall time diagram.
11/18/2010 Changed V
01/13/2011 Removed “Preliminary” status heading.
10/09/09
02/25/11
Date
New Datasheet
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in t
Added t
Changed max I
mA to 61 mA.
Changed V
- 1.15V to V
Removed V
Added R
= 140 kΩ.
Added a measurement definition for C
page 4.
Added V
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 250 MHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to t
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
2, 3, 4, 5 and 7, to be consistent with EROS.
1 and in t
Added note 2 to describe I
Removed reference to data distribution from “Functional Description”.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical
Specs table.
Updated package diagram.
Added Acronyms and Ordering Code Definition.
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Changed C
Removed t
Changed t
swing, 50% input duty cycle measured at Vdd/2”.
Changed phase jitter condition to “156.25 MHz sinewave, 12 kHz to 20 MHz
offset; input swing = 2.2V, V
Removed t
Removed resistors from IN0/IN1 in
Added
Post to external web.
Figure 8
PU
P
PP
JIT
JIT
ODC
spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max
spec to the Operating Conditions table on page 3.
R
S
OH
IN
IN
spec to the AC Electrical Specs table on page 5. V
OD
DD
in the AC Electrical Specs table on page 5.
in the AC Electrical Specs table on page 6.
and t
and t
and V
condition to “Measured at 10 MHz”.
in the DC Electrical Specs table on page 4: minimum from V
from 48/52% to 45/55%, changed condition to “Rail-to-rail input
- 1.20V; maximum from V
spec from the DC Electrical Specs table on page 4.
DD
to describe T
H
F
spec in the DC Electrical Specs table on page 4 from 60
input specs from AC specs table.
specs from AC specs table.
R
OUT
and t
specs from 4.0V to “lesser of 4.0 or V
Description of Change
IH
F
bias
specs in the AC Electrical specs table on page 5
and I
SOE
= V
and T
IL
DD
Logic Block
specs.
/2 “
IN
SOD
in the DC Electrical Specs table on
DD
.
- 0.75V to V
Diagram.
DD
CY2CP1504
- 0.70V.
DD
PP
Page 12 of 13
+ 0.4”
min = 600
DD
[+] Feedback