cy2sstv850oct SpectraLinear Inc, cy2sstv850oct Datasheet - Page 3

• Manufacturer Part Number: cy2sstv850oct
• Description: Differential Clock Buffer/driver
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 21, 2006
Function Table
Power Management
The
CY2SSTV850 allows the user to implement unique power
management schemes into the design. Outputs are
three-stated when disabled through the two-line interface as
individual bits are set low in Byte 0 and Byte 1 registers. The
feedback output pair (FBOUTT, FBOUTC) cannot be disabled
via two-line serial bus. The enabling and disabling of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV850 will likely
be in a nested clock tree application. For these applications
the CY2SSTV850 offers a differential clock input pair as a PLL
reference. The CY2SSTV850 then can lock onto the reference
and translate with near zero delay to low-skew outputs. For
normal operation, the external feedback input, FBINT, is
connected to the feedback output, FBOUTT. By connecting
the feedback output to the feedback input the propagation
delay through the device is eliminated. The PLL works to align
the output edge with the input reference edge thus producing
a near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped low, the PLL is turned off and
bypassed for test purposes.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
“Command Code” byte, and “Byte Count” byte.
2 Line Serial Interface
2-Line Serial Interface Slave Address
Note:
Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes (command code and
the number of bytes), and the data bytes. This sequence is illustrated in the following tables.
3. Each output pair can be three-stated via the two-line serial interface.
AVDD
GND
GND
2.5V
2.5V
2.5V
A7
1
individual
<20 MHz <30 MHZ <20 MHz <30 MHz
Nom
CLKINT
output
A6
H
H
1
L
L
Design
Inputs
enable/disable
A5
0
Nom
CLKINC
H
H
L
L
control
Design
A4
1
of
YT(0:9)
the
Hi-Z
H
H
L
L
A3
0
[3]
Byte0: Output Register (1 = Enable, 0 = Disable)
Byte1: Output Register (1 = Enable, 0 = Disable)
YC(0:9)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Hi-Z
H
H
L
L
Outputs
A2
[3]
0
@Pup
@Pup
FBOUTT
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Hi-Z
H
H
L
L
A1
1
29, 30
27, 26
20, 19
22, 23
46, 47
44, 43
39, 40
10, 9
Pin#
Pin#
3, 2
5, 6
FBOUTC
Hi-Z
H
H
L
L
CY2SSTV850
BYPASSED/OFF
BYPASSED/OFF
Description
Description
YT8, YC8
YT9, YC9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
YT0, YC0
YT1, YC1
YT2, YC2
YT3, YC3
YT4, YC4
YT5, YC5
YT6, YC6
YT7, YC7
Page 3 of 9
R/W
0
PLL
On
On
Off