cy29775 Cypress Semiconductor Corporation., cy29775 Datasheet
cy29775
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cy29775 Summary of contents
Page 1
... The CY29775 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29775 features two reference clock inputs and provides 14 outputs partitioned in 3 banks and 4 outputs. Bank A and Bank B divide the VCO output while Bank C divides ...
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... LVCMOS Frequency select input, Bank (A:C). See Table 4 on page 4. LVCMOS Feedback dividers select inputs. See Table 5 on page 5. VDD 2.5V or 3.3V Power supply for bank A output clocks VDD 2.5V or 3.3V Power supply for bank B output clocks CY29775 V SS QB1 V DDQB QB2 V SS QB3 V DDQB QB4 ...
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... Document #: 38-07480 Rev. *A Type Description VDD 2.5V or 3.3V Power supply for bank C output clocks VDD 2.5V or 3.3V Power supply for feedback output clock VDD 2.5V or 3.3V Power supply for PLL VDD 2.5V or 3.3V Power supply for core and inputs Ground Analog Ground Ground Common Ground No Connection CY29775 [2,3] [2,3] [2,3] [2,3] Page [+] Feedback ...
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... QA(4:0) SELB QB(4: y16 CY29775 Input Frequency Range (AVDD = 2.5V) 25 MHz to 50 MHz 16.6 MHz to 33.3 MHz 12.5 MHz to 25 MHz 8.3 MHz to 16.6 MHz 6.25 MHz to 12.5 MHz 4.2 MHz to 8.3 MHz 50 MHz to 100 MHz 33.3 MHz to 66.6 MHz 25 MHz to 50 MHz 16.6 MHz to 33.3 MHz 1 TCLK1 VCOy4 (low input frequency range) VCO (high input frequency range) PLL enabled ...
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... SS Relative to V –0.3 SS – Functional 200 Ripple Frequency < 100 kHz – Non Functional –65 Functional –40 Functional – Functional – Functional – 2000 Manufacturing test CY29775 FB_OUT y8 y16 y12 y24 y16 y32 y24 y48 y12 Max Unit 5.5 V 3.465 0.3 ...
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... only VDD All V pins except A DD VDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz . Alternatively, each output drives up to two 50: series terminated transmission lines. TT CY29775 Min Typ. Max Unit – – 0.8 V 2.0 – – – 0.55 V – ...
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... TCLK to FB_IN, does not include jitter Skew within Bank Banks at same frequency Banks at different frequency VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies . Parameters are guaranteed by characterization and are not 100% tested. TT CY29775 Min Typ. Max Unit 200 – 400 MHz 50 – 100 MHz 33 ...
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... Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage VCO_SEL = 0 VCO_SEL = 1 Same frequency Multiple frequencies IO at same V DD CY29775 Min Typ. Max Unit 200 – 500 MHz 50 – 125 MHz 33.3 – ...
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... ohm ohm ohm T VTT VDD VDD/2 GND VDD t(I GND Figure 4. Output Duty Cycle (DC) VDD VDD GND 100% Figure 5. Output-to-Output Skew, t sk(O) t SK(O) CY29775 ohm T VTT VDD/2 VDD VDD/2 GND VDD VDD/2 GND Page [+] Feedback ...
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... Package Drawing and Dimension Figure 6. 52-Lead Thin Plastic Quad Flat Pack ( 1.0 mm) A52B Document #: 38-07480 Rev. *A Package Type Product Flow Industrial, –40qC to +85qC Industrial, –40qC to 85qC Industrial, –40qC to +85qC Industrial, –40qC to 85qC CY29775 Status Obsolete Obsolete Active Active 51-85158-** Page [+] Feedback ...
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... Document History Page Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Document #: 38-07480 Rev. ECN No. Issue Date Change ** 125955 04/29/03 *A 1875214 See ECN WWZ/AESA Added Pb-free part numbers and updated device status © Cypress Semiconductor Corporation, 2003-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...