cy29775 Cypress Semiconductor Corporation., cy29775 Datasheet - Page 2

• Manufacturer Part Number: cy29775
• Description: 2.5v Or 3.3v, 200-mhz, 14 Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07480 Rev. *A
Pinouts
Table 1. Pin Definition - 52-Pin 1.0-mm TQFP package
Notes
9
10
16, 18, 21,
23, 25
32, 34, 36,
38, 40
44, 46, 48,
50
29
31
2
3
6
8
11, 52
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
1. PU = Internal pull up, PD = Internal pull down
2. A 0.1-PF bypass capacitor must be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
frequency filtering characteristics is cancelled by the lead inductance of the traces.
pins.
Pin
[1]
TCLK0
TCLK1
QA(4:0)
QB(4:0)
QC(3:0)
FB_OUT
FB_IN
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL(1,0)
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
Name
Figure 1. Pin Diagram - 52-Pin 1.0-mm TQFP package
Supply
Supply
I, PD
I, PU
I, PU
I, PU
I, PU
I, PU
I, PD
I, PD
I, PD
I, PD
IO
O
O
O
O
V CO_SEL1
CLK_STP#
TCLK_SEL
MR#/OE
PLL_EN
TCLK0
TCLK1
SELB
SELC
SELA
A V DD
V SS
V DD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Type
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 18 19 20 21 22 23 24 25 26
CY29775
LVCMOS/LVTTL reference clock input
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
2.5V or 3.3V Power supply for bank A output clocks
2.5V or 3.3V Power supply for bank B output clocks
Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation.
This input must be at the same voltage rail as input reference clock.
See Table 2 on page 4.
Output enable/disable input. See Table 3 on page 4.
Clock stop enable/disable input. See Table 3 on page 4.
PLL enable/disable input. See Table 3 on page 4.
Reference select input. See Table 3 on page 4.
VCO divider select input. See
Frequency select input, Bank (A:C). See Table 4 on page 4.
Feedback dividers select inputs. See Table 5 on page 5.
39
38
37
36
35
34
33
32
31
30
29
28
27
V SS
QB1
V DDQB
QB2
V SS
QB3
V DDQB
QB4
FB_IN
V SS
FB_OUT
V DDFB
NC
Description
Tables 3, 4 and
5.
[2,3]
[2,3]
CY29775
Page 2 of 11
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