cy29774 Cypress Semiconductor Corporation., cy29774 Datasheet - Page 2

• Manufacturer Part Number: cy29774
• Description: 2.5v Or 3.3v, 125-mhz, 14 Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Pin Description
Notes:
Document #: 38-07479 Rev. **
1.
2.
3.
9
10
16, 18, 21,
23, 25
32, 34, 36,
38, 40
44, 46, 48,
50
29
31
2
3
6
8
52
7, 4, 5
20, 14
17, 22, 26
33, 37, 41
45, 49
28
13
12
15
1, 19, 24,
30, 35, 39,
43, 47, 51
11, 27, 42
PU = Internal pull up, PD = Internal pull down
A 0.1- F bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply
pins.
Pin
TCLK0
TCLK1
QA(4:0)
QB(4:0)
QC(3:0)
FB_OUT
FB_IN
MR#/OE
CLK_STP#
PLL_EN
TCLK_SEL
VCO_SEL
SEL(A:C)
FB_SEL(1,0)
VDDQA
VDDQB
VDDQC
VDDFB
AVDD
VDD
AVSS
VSS
NC
Name
[1]
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
I, PD
I, PD
I, PD
I, PU
I, PU
I, PU
I, PU
I, PU
I, PD
I, PD
I/O
O
O
O
O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Ground
Type
VDD
VDD
VDD
VDD
VDD
VDD
LVCMOS/LVTTL reference clock input
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
Output enable/disable input. See Table 2.
Clock stop enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
Reference select input. See Table 2.
VCO divider select input. See Table 2.
Frequency select input, Bank (A:C). See Table 3.
Feedback dividers select input. See Table 4.
2.5V or 3.3V Power supply for bank A output clocks
2.5V or 3.3V Power supply for bank B output clocks
2.5V or 3.3V Power supply for bank C output clocks
2.5V or 3.3V Power supply for feedback output clock
2.5V or 3.3V Power supply for PLL
2.5V or 3.3V Power supply for core and inputs
Analog Ground
Common Ground
No Connection
Description
[2,3]
[2,3]
[2,3]
[2,3]
[2,3]
[2,3]
CY29774
Page 2 of 9
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