cy29774 Cypress Semiconductor Corporation., cy29774 Datasheet - Page 5

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cy29774

Manufacturer Part Number
cy29774
Description
2.5v Or 3.3v, 125-mhz, 14 Output Zero Delay Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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DC Electrical Specifications
AC Electrical Specifications
Note:
Document #: 38-07479 Rev. **
6.
f
f
f
t
f
DC
t
t
t
tsk(B)
t
t
BW
t
t
t
t
sk(O)
VCO
in
refDC
r
MAX
r
( )
PLZ, HZ
PZL, ZH
JIT(CC)
JIT(PER)
JIT( )
LOCK
Parameter
Parameter
, t
, t
AC characteristics apply for parallel output termination of 50 to V
f
f
Z
I
I
DDQ
I
C
DDA
OUT
DD
IN
VCO Frequency
Input Frequency
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
Output Duty Cycle
Output Rise/Fall times
Propagation Delay (static phase
offset)
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth (–3 dB)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
Description
Description
[6]
(V
(V
DD
DD
= 3.3V ± 5%, T
= 2.5V ± 5%, T
A
All V
Outputs loaded @ 100 MHz
VDD
Bypass mode (PLL_EN = 0)
0.7V to 1.7V
0.7V to 1.8V
TCLK to FB_IN, does not
include jitter
Skew within Bank
Banks at same frequency
Banks at different frequency
Same frequency
Multiple frequencies
TT
8 Feedback
12 Feedback
16 Feedback
24 Feedback
32 Feedback
48 Feedback
4 Output
8 Output
12 Output
16 Output
24 Output
A
. Parameters are guaranteed by characterization and are not 100% tested.
DD
= –40°C to +85°C) (continued)
only
A
= –40°C to +85°C)
pins except A
Condition
Condition
VDD
Min.
12
–100
Min.
16.6
12.5
16.6
12.5
200
8.3
6.3
4.2
8.3
0.1
25
25
50
25
45
0
Typ.
225
0.5 - 1.0
15
5
4
Typ.
Max.
10
18
1
Max.
16.6
12.5
16.6
33.3
33.3
400
200
100
100
150
150
225
150
300
100
150
8.3
1.0
1.0
50
25
75
50
25
55
10
10
1
CY29774
Page 5 of 9
Unit
mA
mA
mA
MHz
MHz
MHz
MHz
pF
Unit
ms
ns
ns
ps
ps
ps
ns
ns
ps
ps
ps
%
%
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