cy25566 Cypress Semiconductor Corporation., cy25566 Datasheet
cy25566
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cy25566 Summary of contents
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... DIVIDER DIVIDER & 8 SSCLK1a MUX 9 SSCLK1b VDD SSCLK2 RANGE CONTROL 20 K VSS • 3901 North First Street • San Jose CY25566 XIN/CLKIN 1 16 XOUT REFOFF 2 15 SSCLK2 REFOUT 3 14 VSS VDD VSS VSS ...
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... With a wide range of selectable bandwidths, the CY25566 is a very flexible low-EMI clock. Modulation can be disabled to provide a four-output conventional clock. The CY25566 is available in a 16-pin SOIC (150-mil.) package with a commercial operating temperature range of 0°C to 70°C. Output Clock Architecture ...
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... SSCLK1a/b and SSCLK2. S0 and S1 of the CY25566 are designed to sense three different analog levels. With this tri-level structure, the CY25566 is able to detect 9 different logic states. Refer to tables 5, 6 and 7 for the results of each of these 9 states. The level of each state is defined as follows: Logic State “ ...
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... Then: modulation rate = Fmod = 65 MHz/1166 = 55.7 kHz Modulation Profile Document #: 38-07429 Rev. *B utilize frequency The CY25566 has three frequency groups to select from. Each combination of frequency and bandwidth can be selected by programming the input control lines, S0–S3, to the proper logic state. Group 1 is the 1X low-frequency range and operates from 25 to 100 MHz ...
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... 3.4 2.9 2.8 3.1 2.5 2.4 2.8 2.4 2.3 2.6 2.2 2 1.5 1.2 1.4 1.1 1.3 1.1 1.2 1 3.2 2.8 2.7 3.1 2.6 2.5 2.9 2.5 2.4 2.7 2.2 2 1.6 1.3 1.4 1.1 1.3 1.1 1.3 1.1 1.2 1.0 1.2 1.0 1.2 1.0 1.1 0.9 1.1 0 3.5 3.0 2.6 2.5 3.3 2.9 2.4 2.3 3.1 2.7 2.2 2.1 2.9 2.5 2.1 2.0 CY25566 Page [+] Feedback ...
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... Application Schematic In this example, the CY25566 is being driven by a 75-MHz reference clock and are programmed to select 2.5%. (Refer to Table 1 and 2 and are programmed to select the Group 2 range. 75 MHz Clock source Document #: 38-07429 Rev 3.30 VDC. DD SSCLK1a = 75 MHz @ 2.5% center spread modulation. ...
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... SSCLK1(a+b pF, 100 MHz SSCLK1(a+b pF, 200 MHz SSCLK1(a+b pF, 200 MHz REFOUT, Pin pF, 50 MHz REFOUT, Pin pF, 50 MHz XIN/CLK (Pin) SSCLK1a/b (Pin 8 and 100 MHz, SSCLK1a 200 MHz, SSCLK1a CY25566 Typ. Max. Unit 3.3 3. ...
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... S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 16 SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0°~8° 0.004[0.102] 0.0098[0.249] CY25566 Product Flow MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.016[0.406] 0.0098[0.249] 0.035[0.889] ...
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... Document Title:CY25566 Spread Spectrum Clock Generator Document Number: 38-07429 Issue Rev. ECN No. Date ** 115771 07/01/02 *A 122705 12/30/02 *B 404070 See ECN Document #: 38-07429 Rev. *B Orig. of Description of Change Change OXC New Data Sheet RBI Added power up requirements to maximum ratings information. RGL Minor Change: Typo error on table 1, column (not M) ...