cy25c01 Cypress Semiconductor Corporation., cy25c01 Datasheet - Page 6

• Manufacturer Part Number: cy25c01
• Description: 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, And 16 Kbit X8 Spi Serial Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Read Sequence (READ)
Reading the CY25C01/02/04/08/16 through the Serial Output
(SO) pin requires the following sequence. After the CS line is
pulled low to select a device, the read op-code (including A8) is
transmitted through the SI line followed by the byte address to
be read (A7–A0). When completed, any data on the SI line is
ignored. The data (D7–D0) at the specified address is shifted out
onto the SO line. If only one byte is to be read, the CS line must
be driven high after the data comes out. The read sequence can
be continued since the byte address is automatically incre-
mented and data continues to be shifted out. When the highest
address is reached, the address counter rolls over to the lowest
address allowing the entire memory to be read in one continuous
read cycle.
Write Sequence (WRITE)
To program the CY25C01/02/04/08/16, two separate instructions
must be executed. First, the device must be write enabled
through the WREN instruction. Then a write (WRITE) instruction
can be executed. Also, the address of the memory locations to
be programmed must be outside the protected address field
location selected by the block write protection level. During an
Note
Document #: 001-15633 Rev. *C
2. If the device is not write enabled (WREN), the device ignores the write instruction and return to the standby state, when CS is brought HIGH. A new CS falling edge is
required to re initiate the serial communication.
SCK
SO
CS
SI
[2]
Figure 4. Write Enable (WREN) Instruction Timing
internal write cycle, all commands are ignored except the RDSR
instruction.
The sequence for a write instruction is as follows. After the CS
line is pulled low to select the device, the WRITE op-code is
transmitted throuh the SI line followed by the byte address
(A7–A0) and the data (D7–D0) to be programmed. Programming
starts after the CS pin is brought high. The low to high transition
of the CS pin must occur during the SCK low time immediately
after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device is determined by initi-
ating a read status register (RDSR) instruction. If Bit 0 = ‘1’, the
write cycle is still in progress. If Bit 0 = ‘0’, the write cycle has
ended. Only the RDSR instruction is enabled during the write
programming cycle.
The CY25C01/02/04/08/16 is capable of a 32-byte page write
operation. After each byte of data is received, the five low order
address bits are internally incremented by one; the high order
bits of the address remain constant. If more than 16 bytes of data
are transmitted, the address counter rolls over and the previously
written data is overwritten. The CY25C01/02/04/08/16 is
automatically returned to the write disable state at the completion
of a write cycle. WEN bit is reset after every write instruction
regardless of it belonging to a protected array.
CY25C01/02/04/08/16
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