cy28src01 Cypress Semiconductor Corporation., cy28src01 Datasheet
cy28src01
Related parts for cy28src01
cy28src01 Summary of contents
Page 1
... TSSOP package Pin Configuration VSS_SRC VDD_SRC SRCC0 SRCT0 VDD_SRC VSS_SRC IREF VDD_SRC VSSA SRCT0,SRCC0 • 3901 North First Street • San Jose CY28SRC01 1 16 VDD_SRC 2 15 SDATA 3 14 SCLK 4 13 XOUT 5 12 XIN 6 11 ...
Page 2
... Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). CY28SRC01 Description Page [+] Feedback ...
Page 3
... Bit 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28SRC01 Description Description Page [+] Feedback ...
Page 4
... Enable- only for CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi- Enable SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable- only for CY28SRC01 0 = Disable (Hi-Z Enable Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved ...
Page 5
... Reserved Reserved Reserved Reserved Description REF/N or Tri-state Select 1 = REF/N Clock Tri-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode Normal operation Reserved Reserved Reserved Reserved Reserved Reserved Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 CY28SRC01 Page [+] Feedback ...
Page 6
... Crystal Recommendations The CY28SRC01 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28SRC01 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
Page 7
... JEDEC (JESD 51) At 1/8 in. Condition 3.3V ± 5% SDATA, SCLK SDATA, SCLK V DD Except Pull-ups or Pull downs 0<V < max load and frequency PD asserted, Outputs driven PD asserted, Outputs Hi-Z CY28SRC01 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0 –65 +150 ° ° ...
Page 8
... Math averages Figure 3 See Figure 3. Measure Ω Ω Ω Ω Figure 3. 0.7V Load Configuration CY28SRC01 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns and – 10.0 ...
Page 9
... PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY28SRC01 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page ...
Page 10
... Document History Page Document Title: CY28SRC01 PCI-Express Clock Generator Document Number: 001-00058 REV. ECN NO. Issue Date ** 358561 See ECN *A 375223 See ECN Document #: 001-00058 Rev. *A PRELIMINARY Orig. of Change Description of Change RGL New Data Sheet RGL Byte 0 bit 7 change to RESERVED Byte 6 bit 4 change to RESERVED Changed shunt capacitor from Changed Cl1 and figure from ...