cy28src01 Cypress Semiconductor Corporation., cy28src01 Datasheet - Page 6

• Manufacturer Part Number: cy28src01
• Description: Pci-express Clock Generator
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-00058 Rev. *A
Byte 7: Control Register 7 (continued)
Table 4. Crystal Recommendations
Crystal Recommendations
The CY28SRC01 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28SRC01 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
14.31818 MHz
Frequency
Bit
4
3
2
1
0
(Fund)
Figure 1. Crystal Capacitive Clarification
@Pup
1
1
0
0
0
Cut
AT
Loading
Parallel
Name
12pF - 16pF
Load Cap
PRELIMINARY
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
(max.)
Drive
1mW
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This means the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLe
Cs1
Shunt Cap
(max.)
Total Capacitance (as seen by the crystal)
=
7 pF
Figure 2. Crystal Loading Example
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
C i1
Description
Ce = 2 * CL – (Cs + Ci)
Clock Chip
1
Tolerance
+ 50ppm
XTAL
(max.)
Ci2
+
X2
1
Ce2
Ce2 + Cs2 + Ci2
Stability
+ 50ppm
(max.)
CY28SRC01
Cs2
1
3 to 6p
27pF
Trim
Pin
Page 6 of 10
Trace
2.8pF
(max.)
Aging
5 ppm
)
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