cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 10

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
Byte 8: Control Register 8
Byte 9: Control Register 9
Byte 10: Control Register 10
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
@Pup
@Pup
@Pup
HW
HW
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
PCIF_0_with PCI_STOP# Allows control of PCIF_0 with assertion of PCI_STOP#
TEST_MODE_ENTRY
TEST_MODE_SEL
GCLK_SEL latch
12C_VOUT<2>
12C_VOUT<1>
12C_VOUT<0>
27M_NSS_OE
TME_STRAP
27M_SS_OE
REF_DSC1
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Reserved
Reserved
PLL3_EN
Name
Name
Name
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Reserved
Reserved
Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
Trusted mode enable strap status
0 = Normal, 1 = No overclocking
REF drive strength 1 of 2 (See Byte 17 and 18 for more setting)
0 = Low, 1 = High
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
PLL3 power down
0 = Power down, 1 = Power up
Description
Description
Description
CY28548
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