cy28548 SpectraLinear Inc, cy28548 Datasheet - Page 4

• Manufacturer Part Number: cy28548
• Description: Clock Generator For Intel Crestline Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.5 September 16, 2008
TSSOP Pin Definitions
Pin No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
SRCC11/ CR#_G
SRCT11/ CR#_H
SRCT10
SRCC10
VDD_SRC_IO
CPU_STOP#
PCI_STOP#
VDD_SRC
SRCC6
SRCT6
VSS_SRC
SRCC7/ CR#_E
SRCT7/ CR#_F
VDD_SRC_IO
SRCC8 / CPUC2_ITP
SRCC8 / CPUC2_ITP
NC
VDD_CPU_IO
CPUC1
CPUT1
VSS_CPU
CPUC0
CPUT0
VDD_CPU
CKPWRGD / PWRDWN#
Name
(continued)
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Selectable Complementary differential CPU or SRC clock output.
O, DIF Selectable True differential CPU or SRC clock output.
O, DIF Complementary differential CPU clock outputs.
O, DIF True differential CPU clock outputs.
O, DIF Complementary differential CPU clock outputs.
O, DIF True differential CPU clock outputs.
PWR 3.3V-1.25V Power supply for outputs.
PWR 3.3V Power supply for SRC PLL.
PWR 3.3V-1.25V power supply for outputs.
PWR 3.3V-1.25V Power supply for outputs.
PWR 3.3V Power supply for CPU PLL.
Type
GND
GND
I/O,
DIF
I/O,
DIF
I/O,
DIF
I/O,
DIF
NC
I
I
I
Complementary 100 MHz differential serial reference clocks/3.3V CR#_G
Input Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
True 100 MHz differential serial reference clocks/3.3V CR#_H Input Selected
via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
Ground for outputs.
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input. Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
True 100 MHz differential serial reference clocks/3.3V CR#_FInput.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
No connect.
Note that CPU1 is the iAMT clock and is on in that mode.
Note that CPU1 is the iAMT clock and is on in that mode.
Ground for outputs.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
3.3V-tolerant input for stopping CPU outputs
Description
CY28548
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