cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 3

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Table 1. Frequency Select Table (FS_A FS_B FS_C)
Frequency Select Pins (FS_A, FS_B, FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, and FS_C inputs prior
to VTT_PWRGD# assertion (as seen by the clock synthe-
sizer). Upon VTT_PWRGD# being sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, and FS_C values. For all logic
levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored. There is
one CPU frequency select table based on the CK410 specifi-
cation.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Command Code Definition
Table 3. Block Read and Block Write Protocol
FS_C
27:20
36:29
45:38
18:11
(6:5)
(4:0)
1
0
0
0
0
1
1
1
8:2
Bit
Bit
10
19
28
37
1
9
7
FS_B
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
0 = Block read or block write operation, 1 = Byte read or byte write operation
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
0
0
1
1
0
0
1
1
Block Write Protocol
FS_A
1
1
1
0
0
0
0
1
Description
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
CPU
INFORMATION
ADVANCE
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
SRC
Description
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
27:21
37:30
18:11
8:2
Bit
10
19
20
28
29
1
9
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
RESERVED
ATIG
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Block Read Protocol
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF0
Description
CY28RS600-2
Page 3 of 17
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
USB