cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 5

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Byte 1: Output Enable Register 1
Byte 2: Output Enable Register 2
Byte 3: SW_FREQ Selection Register
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
HW
HW
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
CPU Spread Enable
ATIG_OC_SEL1
ATIG_OC_SEL0
ATIG[T/C]3
ATIG[T/C]2
ATIG[T/C]1
ATIG[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
USB_48_1
USB_48_0
Reserved
Reserved
Reserved
FSEL_C
FSEL_B
FSEL_A
REF_2
REF_1
REF_0
Name
Name
Name
FSC
FSB
FSA
INFORMATION
ADVANCE
Reserved
Reserved
ATIG[T/C]3 Output Enable
ATIG[T/C]2 Output Enable
ATIG[T/C]1 Output Enable
ATIG[T/C]0 Output Enable
CPU[T/C]2 Output Enable
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
USB_48_1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
USB_48_0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF_0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved
CPU_PLL (PLL1) Spread Spectrum Enable
0= Spread Off, 1 = Spread On
Read Only bit which reflects the value of pin 62 @ VTTPWRGD# assertion
Read Only bit which reflects the value of pin 61 @ VTTPWRGD# assertion
Read Only bit which reflects the value of pin 60 @ VTTPWRGD# assertion
SW Frequency Selection Bits
SEL1
X
0
1
SEL0
0
0
1
111.33–167 MHz
100–125 MHz
166–256 MHz
ATIG Output
Description
Description
Description
CY28RS600-2
167–250
200–250
167–256
N
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