ds2152 Maxim Integrated Products, Inc., ds2152 Datasheet - Page 22
ds2152
Manufacturer Part Number
ds2152
Description
Ds2152 Enhanced T1 Single Chip Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2152.pdf
(97 pages)
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex)
Table 4-1. Output Pin Test Modes
(MSB)
TEST1
TEST 1
SYMBOL
TD4YM
TZBTSI
TEST1
TEST0
TB7ZS
TSDW
0
0
1
1
TSIO
TSM
TEST0
TEST 0
0
1
0
1
POSITION
TCR2.7
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
TCR2.1
TCR2.0
TZBTSI
Operate normally
Force all output pins tri-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
NAME AND DESCRIPTION
Test Mode Bit 1 for Output Pins. See
Test Mode Bit 0 for Output Pins. See
Transmit Side ZBTSI Enable.
0 = ZBTSI disabled
1 = ZBTSI enabled
TSYNC Double-Wide. (Note: this bit must be set to 0 when
TCR2.3 = 1 or when TCR2.2 = 0.)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
TSYNC Mode Select.
0 = frame mode (see the timing diagrams in Section 16)
1 = multiframe mode (see the timing diagrams in Section 16)
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
Transmit Side D4 Yellow Alarm Select.
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
Transmit Side Bit 7 Zero Suppression Enable.
0 = no stuffing occurs
1 = Bit 7 force to a 1 in channels with all 0s
TSDW
22 of 97
EFFECT ON OUTPUT PINS
TSM
TSIO
Table
Table
TD4YM
4-1.
4-1.
TB7ZS
(LSB)